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Cleanup of ECC modules & SRAM
ci #77: Pull request #22 synchronize by micprog
May 2, 2024 12:50 1m 46s michaero/cleanup
May 2, 2024 12:50 1m 46s
Cleanup of ECC modules & SRAM
ci #76: Pull request #22 synchronize by micprog
May 2, 2024 12:28 1m 47s michaero/cleanup
May 2, 2024 12:28 1m 47s
Cleanup of ECC modules & SRAM
ci #75: Pull request #22 opened by micprog
May 2, 2024 12:12 21s michaero/cleanup
May 2, 2024 12:12 21s
Add sram update by a sram read
ci #70: Pull request #20 synchronize by Aquaticfuller
April 16, 2024 23:14 1m 47s zx/corrected_data_sram_update
April 16, 2024 23:14 1m 47s
Fix ECC synthesizability (#18)
ci #67: Commit a466340 pushed by micprog
February 19, 2024 11:50 1m 28s master
February 19, 2024 11:50 1m 28s
Fix ECC synthesizability
ci #66: Pull request #18 synchronize by micprog
February 19, 2024 10:25 1m 18s michaero/fix-ecc
February 19, 2024 10:25 1m 18s
Fix ECC synthesizability
ci #65: Pull request #18 synchronize by micprog
February 13, 2024 13:21 1m 46s michaero/fix-ecc
February 13, 2024 13:21 1m 46s
Fix ECC synthesizability
ci #64: Pull request #18 synchronize by micprog
February 13, 2024 12:46 1m 50s michaero/fix-ecc
February 13, 2024 12:46 1m 50s
Fix ECC synthesizability
ci #63: Pull request #18 opened by micprog
February 13, 2024 12:18 1m 49s michaero/fix-ecc
February 13, 2024 12:18 1m 49s
Merge pull request #16 from pulp-platform/sv_hsiao
ci #62: Commit d949340 pushed by micprog
January 19, 2024 18:17 1m 18s master
January 19, 2024 18:17 1m 18s
Add SystemVerilog Hsiao modules
ci #61: Pull request #16 synchronize by micprog
January 19, 2024 18:15 1m 39s sv_hsiao
January 19, 2024 18:15 1m 39s
Fix broken url (#10)
ci #60: Commit 2739fc2 pushed by micprog
January 19, 2024 18:12 1m 25s master
January 19, 2024 18:12 1m 25s
Add SystemVerilog Hsiao modules
ci #59: Pull request #16 synchronize by micprog
January 17, 2024 16:49 1m 40s sv_hsiao
January 17, 2024 16:49 1m 40s
Add SystemVerilog Hsiao modules
ci #58: Pull request #16 synchronize by micprog
January 17, 2024 14:23 1m 36s sv_hsiao
January 17, 2024 14:23 1m 36s
Add SystemVerilog Hsiao modules
ci #57: Pull request #16 synchronize by micprog
January 17, 2024 14:17 1m 33s sv_hsiao
January 17, 2024 14:17 1m 33s
Add SystemVerilog Hsiao modules
ci #56: Pull request #16 synchronize by micprog
January 17, 2024 09:22 1m 29s sv_hsiao
January 17, 2024 09:22 1m 29s
Add SystemVerilog Hsiao modules
ci #55: Pull request #16 synchronize by micprog
January 16, 2024 17:56 1m 18s sv_hsiao
January 16, 2024 17:56 1m 18s
Add SystemVerilog Hsiao modules
ci #54: Pull request #16 synchronize by micprog
January 16, 2024 13:11 1m 17s sv_hsiao
January 16, 2024 13:11 1m 17s
Add SystemVerilog Hsiao modules
ci #53: Pull request #16 synchronize by micprog
January 16, 2024 13:08 1m 17s sv_hsiao
January 16, 2024 13:08 1m 17s
Add SystemVerilog Hsiao modules
ci #52: Pull request #16 opened by micprog
January 15, 2024 18:15 1m 23s sv_hsiao
January 15, 2024 18:15 1m 23s
Add HMR Unit
ci #51: Pull request #15 synchronize by micprog
January 10, 2024 15:19 1m 29s michaero/hmr-cleanup
January 10, 2024 15:19 1m 29s
Add HMR Unit
ci #50: Pull request #15 synchronize by micprog
January 10, 2024 13:51 1m 35s michaero/hmr-cleanup
January 10, 2024 13:51 1m 35s
Add HMR Unit
ci #49: Pull request #15 synchronize by micprog
January 10, 2024 13:37 1m 42s michaero/hmr-cleanup
January 10, 2024 13:37 1m 42s
Add HMR Unit
ci #48: Pull request #15 synchronize by micprog
January 10, 2024 13:21 1m 36s michaero/hmr-cleanup
January 10, 2024 13:21 1m 36s