Add SystemVerilog Hsiao modules #57
micprogci.yml
on: pull_request
check-stale
26s
lint-verilog
45s
Annotations
2 warnings
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[verible-verilog-lint] rtl/hsiao_ecc/hsiao_ecc_cor.sv#L32:
rtl/hsiao_ecc/hsiao_ecc_cor.sv#L32
Line length exceeds max: 100; is: 117 [Style: line-length] [line-length]
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[verible-verilog-lint] rtl/hsiao_ecc/hsiao_ecc_dec.sv#L32:
rtl/hsiao_ecc/hsiao_ecc_dec.sv#L32
Line length exceeds max: 100; is: 117 [Style: line-length] [line-length]
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verible-linter
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