Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Add SystemVerilog Hsiao modules #16

Merged
merged 5 commits into from
Jan 19, 2024
Merged

Add SystemVerilog Hsiao modules #16

merged 5 commits into from
Jan 19, 2024

Conversation

micprog
Copy link
Member

@micprog micprog commented Jan 15, 2024

No description provided.

@micprog micprog requested a review from yvantor January 15, 2024 18:15
Copy link

@yvantor yvantor left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Looks good to me.

@micprog micprog force-pushed the sv_hsiao branch 6 times, most recently from 3379265 to 71f51ae Compare January 17, 2024 16:49
@micprog micprog merged commit d949340 into master Jan 19, 2024
3 checks passed
@micprog micprog deleted the sv_hsiao branch January 19, 2024 18:17
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

2 participants