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Add SystemVerilog Hsiao modules #16

Merged
merged 5 commits into from
Jan 19, 2024
Merged

Add SystemVerilog Hsiao modules #16

merged 5 commits into from
Jan 19, 2024

Commits on Jan 19, 2024

  1. Add SystemVerilog Hsiao modules

    @micprog
    micprog committed Jan 19, 2024
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  2. Fix hsiao vector selection for ideal set

    @micprog
    micprog committed Jan 19, 2024
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  3. Update lowrisc secded IP

    @micprog
    micprog committed Jan 19, 2024
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  4. Add documentation

    @micprog
    micprog committed Jan 19, 2024
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  5. Fix tb_ecc_scrubber

    @micprog
    micprog committed Jan 19, 2024
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