Add SystemVerilog Hsiao modules #55
micprogci.yml
on: pull_request
check-stale
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lint-verilog
40s
Annotations
4 warnings
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[verible-verilog-lint] rtl/hsiao_ecc/hsiao_ecc_enc.sv#L45:
rtl/hsiao_ecc/hsiao_ecc_enc.sv#L45
All generate block statements must have a label [Style: generate-statements] [generate-label]
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[verible-verilog-lint] rtl/hsiao_ecc/hsiao_ecc_cor.sv#L56:
rtl/hsiao_ecc/hsiao_ecc_cor.sv#L56
All generate block statements must have a label [Style: generate-statements] [generate-label]
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[verible-verilog-lint] rtl/hsiao_ecc/hsiao_ecc_dec.sv#L56:
rtl/hsiao_ecc/hsiao_ecc_dec.sv#L56
All generate block statements must have a label [Style: generate-statements] [generate-label]
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[verible-verilog-lint] rtl/hsiao_ecc/hsiao_ecc_pkg.sv#L100:
rtl/hsiao_ecc/hsiao_ecc_pkg.sv#L100
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
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