openroad

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Here are 45 public repositories matching this topic...

google / skywater-pdk

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Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

magic asic eda pdk asic-library openroad openram skywater

Updated Oct 28, 2024
Python

The-OpenROAD-Project / OpenROAD

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OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

cpp tcl eda rtl verilog def gdsii timing-analysis openroad lef opendb-database

Updated Oct 31, 2024
Verilog

The-OpenROAD-Project / OpenLane

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OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

magic asic rtl verilog vlsi foundry yosys klayout caravel netgen system-on-chip openroad openram skywater 130nm soc-design rtl2gds

Updated Oct 20, 2024
Python

google / gf180mcu-pdk

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PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).

asic eda pdk openroad 180nm globalfoundries gf180mcu

Updated May 31, 2023
Makefile

The-OpenROAD-Project / OpenROAD-flow-scripts

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OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

tcl eda rtl verilog def gdsii timing-analysis openroad lef opendb-database

Updated Oct 31, 2024
Verilog

efabless / caravel

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Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.

magic yosys caravel picorv32 openroad vexriscv openram sky130

Updated Sep 14, 2024
Verilog

efabless / openlane2

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The next generation of OpenLane, rewritten from scratch with a modular architecture

flow asic eda verilog vlsi pnr silicon lvs flows sta gdsii drc pdk openroad openlane sky130 gf180mcu rtl-to-gds

Updated Oct 29, 2024
Python

efabless / caravel_mpw-one

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Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

magic yosys caravel picorv32 openroad openram sky130

Updated Feb 22, 2022
Verilog

google / open-source-pdks

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Index of the fully open source process design kits (PDKs) maintained by Google.

asic eda silicon pdk openroad skywater 130nm sky130 180nm globalfoundries gf180mcu

Updated Sep 4, 2022

google / globalfoundries-pdk-libs-gf180mcu_fd_pr

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Primitives for GF180MCU provided by GlobalFoundries.

asic eda pdk openroad 180nm globalfoundries gf180mcu

Updated Aug 28, 2023
Python

daquintero / piel

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Photonic Integrated ELectronics. Microservices to codesign photonics, electronics, quantum, and more.

system electronics optimization quantum codesign photonics openroad gdsfactory

Updated Oct 24, 2024
Python

google / skywater-pdk-libs-sky130_fd_pr_reram

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SKY130 ReRAM and examples (SkyWater Provided)

asic eda silicon ngspice xyce pdk openroad reram skywater 130nm

Updated Apr 20, 2022

google / globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0

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7 track standard cells for GF180MCU provided by GlobalFoundries.

asic eda pdk openroad 180nm standard-cells globalfoundries gf180mcu

Updated Dec 1, 2022
Verilog

google / globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0

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9 track standard cells for GF180MCU provided by GlobalFoundries.

asic eda pdk openroad 180nm standard-cells globalfoundries gf180mcu

Updated Dec 5, 2022
Verilog

google / globalfoundries-pdk-ip-gf180mcu_fd_ip_sram

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SRAM macros created for the GF180MCU provided by GlobalFoundries.

asic eda ip sram pdk openroad 180nm globalfoundries gf180mcu

Updated Apr 10, 2023
Verilog

aasthadave9 / Advanced-Physical-Design-Using-OpenLANE-Sky130

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This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an opensource RTL2GDS flow using OpenLANE and opensource PDK provided by Google/SkyWater130

linux open-source asic hardware vlsi-physical-design openroad rtl2gds openlane sky130