Skip to content
@efabless

Efabless

Pinned Loading

  1. caravel_user_project caravel_user_project Public template

    https://caravel-user-project.readthedocs.io

    Verilog 186 330

  2. caravel_user_project_analog caravel_user_project_analog Public template

    Verilog 45 89

  3. mpw_precheck mpw_precheck Public

    Python 36 24

  4. caravel caravel Public

    Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.

    Verilog 297 69

  5. caravel_board caravel_board Public

    C 31 41

  6. openframe_timer_example openframe_timer_example Public

    Forked from efabless/caravel_openframe_project

    Example digital project for the Efabless Caravel "openframe" harness

    Verilog 4 4

Repositories

Showing 10 of 216 repositories
  • IHP-Open-PDK Public Forked from IHP-GmbH/IHP-Open-PDK

    130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design

    efabless/IHP-Open-PDK’s past year of commit activity
    HTML 0 Apache-2.0 65 1 1 Updated Dec 11, 2024
  • openlane-metrics Public

    Repository to store metric results for OpenLane 2.0.0+

    efabless/openlane-metrics’s past year of commit activity
    0 0 0 0 Updated Dec 11, 2024
  • openlane2 Public

    The next generation of OpenLane, rewritten from scratch with a modular architecture

    efabless/openlane2’s past year of commit activity
    Python 225 Apache-2.0 41 73 18 Updated Dec 11, 2024
  • caravel Public

    Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.

    efabless/caravel’s past year of commit activity
    Verilog 297 Apache-2.0 69 98 16 Updated Dec 10, 2024
  • caravel_user_project_analog Public template
    efabless/caravel_user_project_analog’s past year of commit activity
    Verilog 45 Apache-2.0 89 6 5 Updated Dec 10, 2024
  • openlane2-step-unit-tests Public

    Step-specific Unit Tests for OpenLane 2.0.0+

    efabless/openlane2-step-unit-tests’s past year of commit activity
    Verilog 0 Apache-2.0 0 0 1 Updated Dec 9, 2024
  • caravel-sim-infrastructure Public
    efabless/caravel-sim-infrastructure’s past year of commit activity
    HTML 1 Apache-2.0 4 2 0 Updated Dec 9, 2024
  • cace Public

    Circuit Automatic Characterization Engine

    efabless/cace’s past year of commit activity
    Python 45 Apache-2.0 6 23 1 Updated Dec 6, 2024
  • nix-eda Public

    Nix derivations for EDA tools

    efabless/nix-eda’s past year of commit activity
    Nix 8 Apache-2.0 3 1 0 Updated Dec 5, 2024
  • caravel_mgmt_soc_litex Public

    https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/

    efabless/caravel_mgmt_soc_litex’s past year of commit activity
    Verilog 26 Apache-2.0 15 23 14 Updated Dec 4, 2024
View all repositories

Top languages

Loading…

Most used topics

Loading…