Efabless

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216 repositories

IHP-Open-PDK
Public
130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design
HTML
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Apache License 2.0
•65•0•1•0•Updated Dec 11, 2024Dec 11, 2024
caravel_user_project
Public template
https://caravel-user-project.readthedocs.io
Verilog
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Apache License 2.0
•330•186•85•24•Updated Dec 11, 2024Dec 11, 2024
openlane-metrics
Public
Repository to store metric results for OpenLane 2.0.0+
0•0•0•0•Updated Dec 11, 2024Dec 11, 2024
openlane2
Public
The next generation of OpenLane, rewritten from scratch with a modular architecture
flow asic eda verilog vlsi pnr silicon lvs flows sta
Python
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Apache License 2.0
•41•225•73•18•Updated Dec 11, 2024Dec 11, 2024
caravel
Public
Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.
magic yosys caravel picorv32 openroad vexriscv openram sky130
Verilog
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Apache License 2.0
•69•297•98•14•Updated Dec 10, 2024Dec 10, 2024
caravel_user_project_analog
Public template
Verilog
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Apache License 2.0
•89•45•6•5•Updated Dec 10, 2024Dec 10, 2024
openlane2-step-unit-tests
Public
Step-specific Unit Tests for OpenLane 2.0.0+
Verilog
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Apache License 2.0
•0•0•0•1•Updated Dec 9, 2024Dec 9, 2024
caravel-sim-infrastructure
Public
HTML
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Apache License 2.0
•4•1•2•0•Updated Dec 9, 2024Dec 9, 2024
cace
Public
Circuit Automatic Characterization Engine
Python
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Apache License 2.0
•6•45•23•1•Updated Dec 6, 2024Dec 6, 2024
nix-eda
Public
Nix derivations for EDA tools
nix eda electronic-design-automation nix-flake
Nix
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Apache License 2.0
•3•8•1•0•Updated Dec 5, 2024Dec 5, 2024
caravel_mgmt_soc_litex
Public
https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/
Verilog
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Apache License 2.0
•15•26•22•14•Updated Dec 4, 2024Dec 4, 2024
chipcraft---mest-course
Public
TL-Verilog
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Creative Commons Zero v1.0 Universal
•9•29•0•0•Updated Dec 2, 2024Dec 2, 2024
sky130_pa_ip__instramp
Public
Instrumentation amplifier in sky130 by Phil Allen
Tcl
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Apache License 2.0
•2•2•0•0•Updated Dec 2, 2024Dec 2, 2024
EF_PSRAM_CTRL_V2
Public
Verilog
•
Apache License 2.0
•0•1•3•0•Updated Nov 27, 2024Nov 27, 2024
ipm
Public
Open-source IPs Package Manager (IPM)
Python
•
Apache License 2.0
•2•14•6•2•Updated Nov 27, 2024Nov 27, 2024
sky130_ef_ip__adc3v_12bit
Public
12-bit ADC using other analog component repositories for the sample & hold, DAC, and comparator.
Verilog
•
Apache License 2.0
•2•0•0•0•Updated Nov 27, 2024Nov 27, 2024
sky130_ef_ip__ccomp3v
Public
Continuous analog comparator, 1mV resolution
Tcl
•
Apache License 2.0
•2•0•0•0•Updated Nov 27, 2024Nov 27, 2024
sky130_ef_ip__cdac3v_12bit
Public
12-bit capacitive DAC
Tcl
•2•0•0•0•Updated Nov 27, 2024Nov 27, 2024
sky130_ef_ip__analog_switches
Public
Set of analog switch circuits for general-purpose use
Shell
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Apache License 2.0
•2•0•0•0•Updated Nov 27, 2024Nov 27, 2024
sky130_ef_ip__samplehold
Public
Analog 3.3V sample and hold circuit, with buffered output
Tcl
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Apache License 2.0
•2•0•0•0•Updated Nov 27, 2024Nov 27, 2024
sky130_ef_ip__template
Public template
A template repository for analog designs to ensure consistency and interoperability between IP blocks.
Apache License 2.0
•0•0•0•0•Updated Nov 27, 2024Nov 27, 2024
skywater-pdk-libs-sky130_fd_pr
Public
Python
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Apache License 2.0
•23•6•7•0•Updated Nov 27, 2024Nov 27, 2024
tt-fpga-hdl-demo
Public template
Python
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Apache License 2.0
•6•1•0•0•Updated Nov 27, 2024Nov 27, 2024
cace-action
Public
GitHub composite action for CACE
Apache License 2.0
•0•0•0•0•Updated Nov 26, 2024Nov 26, 2024
sky130_ef_ip__opamp
Public
Instrumentation amplifier (analog IP example)
Verilog
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Apache License 2.0
•4•0•0•0•Updated Nov 26, 2024Nov 26, 2024
EF_SRAM_4096x8
Public
0•0•0•0•Updated Nov 22, 2024Nov 22, 2024
sky130_sw_ip__por
Public
Chipalooza challenge - bandgap-referenced Power-on-Reset (PoR)
Shell
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Apache License 2.0
•2•1•0•1•Updated Nov 21, 2024Nov 21, 2024
sky130_icrg_ip__ulpcomp
Public
Participating IP: ULP Comparator. Designed as part of Efabless latest Caravel design.
Tcl
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Apache License 2.0
•3•2•0•0•Updated Nov 21, 2024Nov 21, 2024
sky130_ak_ip__comparator
Public
Comparator in sky130 by Andrew Kang (Chipalooza challenge 2024)
Shell
•2•0•0•0•Updated Nov 21, 2024Nov 21, 2024
sky130_iic_ip__audiodac_v1
Public
Delta-sigma audio DAC (16b, 48kHz), intended for tape-out on MPW-5, SKY130 technology.
Verilog
•
Apache License 2.0
•5•1•0•1•Updated Nov 20, 2024Nov 20, 2024