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Pull requests: efabless/caravel_mgmt_soc_litex
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Remove in correct double declaration of reg_debug_2 and reg_debug_1 defs.h
#134
opened Dec 4, 2023 by
M0stafaRady
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Added an initialization loop to the SPI flash emulation module
#133
opened Nov 15, 2023 by
RTimothyEdwards
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2nd attempt to push the simulation of caravan I/O and the
simulation
Verilog testbenches and simulation
#104
opened Oct 20, 2022 by
RTimothyEdwards
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In verilog model of standard cells, fix "notifier" register definition
flow
Changes to Makefile and process flow
invalid
This doesn't seem right
#39
opened Jul 8, 2022 by
derekcom17
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Wishbone test
duplicate
This issue or pull request already exists
invalid
This doesn't seem right
#33
opened Mar 23, 2022 by
suppamax
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extended irq test
flow
Changes to Makefile and process flow
simulation
Verilog testbenches and simulation
#31
opened Mar 21, 2022 by
suppamax
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verilog/dv/make: fix typo in comments
flow
Changes to Makefile and process flow
#28
opened Mar 17, 2022 by
proppy
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Fix DFFRAM when building non gate level tests
error
Something isn't working
RTL
Changes to verilog source
#18
opened Feb 18, 2022 by
antonblanchard
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