- About
- Day 1: Inception of Opensource EDA
- Day 2: Floorplanning and library cells
- Day 3: Design library cell
- Day 4: Timing Analysis & CTS
- Day 5: Final steps in RTL2GDS
- Differences from older OpenLANE versions
- Future Scope
- References
OpenLANE is an opensource tool or flow used for opensource tape-outs. The OpenLANE flow comprises a variety of tools such as Yosys, ABC, OpenSTA, Fault, OpenROAD app, Netgen and Magic which are used to harden chips and macros, i.e. generate final GDSII from the design RTL. The primary goal of OpenLANE is to produce clean GDSII with no human intervention. OpenLANE has been tuned to function for the Google-Skywater130 Open Process Design Kit.
The RISC-V Instruction Set Architecture (ISA) is a language used to talk to computers whose hardware is based on RISC-V core. If a user wishes to run a certain application software on a computer, its corresponding C/C++/Java program must be converted into instructions by the compliler. The ouput of the compiler is hardware dependent. These instructions go as inputs to the assembler which outputs binary language that the hardware logic in the chip layout can make sense of. According the the bits received, the digital logic consisting of gates performs the function required by the user of the application software.
The design of digital Application Specific Integrated Circuit (ASIC) requires three enablers or elements - Resistor Transistor Logic Intellectual Property (RTL IPs), Electronic Design Automation (EDA) Tools and Process Design Kit (PDK) data.
- Opensource RTL Designs: github, librecores, opencores
- Opensource EDA tools: QFlow, OpenROAD, OpenLANE
- Opensource PDK data: Google Skywater130 PDK
The ASIC flow objective is to convert RTL design to GDSII format used for final layout. The flow is essentially a software also known as automated PnR (Place & route).
- Synthesis: RTL Converted to gate level netlist using standard cell libraries (SCL)
- Floor & Power Planning: Planning of silicon area to ensure robust power distribution
- Placement: Placing cells on floorplan rows aligned with sites
- Global Placement: for optimal position of cells
- Detailed Placement: for legal positions
- Routing: Valid patterns for wires
- Signoff: Physical (DRC, LVS) and Timing verifications (STA)
OpenLANE utilises a variety of opensource tools in the execution of the ASIC flow:
| Task | Tool/s |
|---|---|
| RTL Synthesis & Technology Mapping | yosys, abc |
| Floorplan & PDN | init_fp, ioPlacer, pdn and tapcell |
| Placement | RePLace, Resizer, OpenPhySyn & OpenDP |
| Static Timing Analysis | OpenSTA |
| Clock Tree Synthesis | TritonCTS |
| Routing | FastRoute and TritonRoute |
| SPEF Extraction | SPEF-Extractor |
| DRC Checks, GDSII Streaming out | Magic, Klayout |
| LVS check | Netgen |
| Circuit validity checker | CVC |
The openLANE file structure looks something like this:
- skywater-pdk: contains PDK files provided by foundry
- open_pdks: contains scripts to setup pdks for opensource tools
- sky130A: contains sky130 pdk files
Openlane can be invoked using docker command followed by opening an interactive session. flow.tcl is a script that specifies details for openLANE flow.
docker
./flow.tcl -interactive
package require openlane 0.9
This project is based on the reference SoC design of PicoRV32 which is a CPU core that implements RISC-V instruction set. Various packages are initialized followed by preparation of the picorv32a design.
prep -design picorv32a
A "runs" folder is generated within the picorv32a folder.
Since today's date is 30th June, a folder titled "30-06..." is created within the picorv32a directory:
The merged file is created during the merging operation in the pircorv32a design preparation (it merges lef and techlef files)
Merged.lef looks something like this:
Next, we run the synthesis of picorv32a design in the openlane interactive terminal:
run_synthesis
The yosys and ABC tools are utilised to convert RTL to gate level netlist
Calcuation of Flop Ratio:
Flop ratio = Number of D Flip flops
______________________
Total Number of cells
dfxtp_4 = 1613,
Number of cells = 14876,
Flop ratio = 1613/14876 = 0.1084 = 10.84%
We may check the success of the synthesis step by checking the synthesis folder for the synthesised netlist file (.v file)
The synthesis statistics report can be accessed within the reports directory. It is usually the last yosys file since files are listed chronologically by date of modification
Two parameters are of importance when it comes to floorplanning namely, Utilisation Factor and Aspect Ratio. They are defined as follows:
Utilisation Factor = Area occupied by netlist
__________________________
Total area of core
Aspect Ratio = Height
________
Width
A Utilisation Factor of 1 signifies 100% utilisation leaving no space for extra cells such as buffer. However, practically, the Utilisation Factor is 0.5-0.6. Likewise, an Aspect ratio of 1 implies that the chip is square shaped. Any value other than 1 implies rectanglular chip.
Once the Utilisation Factor and Aspect Ratio has been decided, the locations of pre-placed cells need to be defined. Pre-placed cells are IPs comprising large combinational logic which once placed maintain a fixed position. Since they are placed before placement and routing, the are known as pre-placed cells.
Pre-placed cells must then be surrounded with decoupling capacitors (decaps). The resistances and capacitances associated with long wire lengths can cause the power supply voltage to drop significantly before reaching the logic circuits. This can lead to the signal value entering into the undefined region, outside the noise margin range. Decaps are huge capacitors charged to power supply voltage and placed close the logic circuit. Their role is to decouple the circuit from power supply by supplying the necessary amount of current to the circuit. They pervent crosstalk and enable local communication
Each block on the chip, however, cannot have its own decap unlike the pre-placed macros. Therefore a good power planning ensures that each block has its own VDD and VSS pads connected to the horizontal and vertical power and GND lines which form a power mesh.
The netlist defines connectivity between logic gates. The place between the core and die is utilised for placing pins. The connectivity information coded in either VHDL or Verilog is used to determine the position of I/O pads of various pins. Then, logical placement blocking of pre-placed macros is performed so as to differentiate that area from that of the pin area.
Files of importance in increasing priority order:
floorplan.tcl- System default envrionment variablesconifg.tclsky130A_sky130_fd_sc_hd_config.tcl
Floorplan envrionment variables or switches:
FP_CORE_UTIL- floorplan core utilisationFP_ASPECT_RATIO- floorplan aspect ratioFP_CORE_MARGIN- Core to die margin areaFP_IO_MODE- defines pin configurations (1 = equidistant/0 = not equidistant)FP_CORE_VMETAL- vertical metal layerFP_CORE_HMETAL- horizontal metal layer
Note: Usually, vertical metal layer and horizontal metal layer values will be 1 more than that specified in the files
To run the picorv32a floorplan in openLANE:
run_floorplan
Post the floorplan run, a .def file will have been created within the results/floorplan directory. We may review floorplan files by checking the floorplan.tcl. The system defaults will have been overriden by switches set in conifg.tcl and further overriden by switches set in sky130A_sky130_fd_sc_hd_config.tcl.
To view the floorplan, Magic is invoked after moving to the results/floorplan directory:
magic -T /home/aastha/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.floorplan.def &
One can zoom into Magic layout by selecting an area with left and right mouse clcik followed by pressing "z" key. Here, equidistant input pins (FP_IO_MODE = 1) can be viewed:
Various components can be identified by using the what command in tkcon window after making a selection on the component:
Zooming in also provides a view of decaps present in picorv32a chip:
The standard cell can be found at the bottom left corner:
The next step in the OpenLANE ASIC flow is placement. The synthesized netlist is the be placed on the floorplan. Placement is perfomed in 2 stages:
- Global Placement: It finds optimal position for all cells which may not be legal and cells may overlap. Optimization is done through reduction of half parameter wire length
- Detailed Placement: It alters the position of cells post global placement so as to legalise them
Legalisation of cells is important from timing point of view.
Congestion aware placement using RePIAce:
run_placement
The objective of placement is the convergence of overflow value. If overflow value progressively reduces during the placement run it implies that the design will converge and placement will be successful. Post placement, the design can be viewed on magic within results/placement directory:
magic -T /home/aastha/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.placement.def &
Zoomed-in views of the standard cell placement:
Note: Power distribution network generation is usually a part of the floorplan step. However, in the openLANE flow, floorplan does not generate PDN. The steps are - floorplan, placement CTS and then PDN
Standard cell design flow involves the following:
- Inputs: PDKs, DRC & LVS rules, SPICE models, libraries, user-defined specifications
- Design steps: Circuit design, Layout design (Art of layout Euler's path and stick diagram), Extraction of parasitics, Characterization (timing, noise, power)
- Outputs: CDL (circuit description language), LEF, GDSII, extracted SPICE netlist (.cir), timing, noise and power .lib files
A typical standard cell characterization flow includes the following steps:
- Read in the models and tech files
- Read extracted spice netlist
- Recognise behaviour of the cell
- Read the subcircuits
- Attach power sources
- Apply stimulus to characterization setup
- Provide necessary output capacitance loads
- Provide necessary simulation commands
The opensource software called GUNA can be used for characterization. Steps 1-8 are fed into the GUNA software which generates timing, noise and power models.
| Timing defintion | Value |
|---|---|
| slew_low_rise_thr | 20% value |
| slew_high_rise_thr | 80% value |
| slew_low_fall_thr | 20% value |
| slew_high_fall_thr | 80% value |
| in_rise_thr | 50% value |
| in_fall_thr | 50% value |
| out_rise_thr | 50% value |
| out_fall_thr | 50% value |
rise delay = time(out_fall_thr) - time(in_rise_thr)
Fall transition time: time(slew_high_fall_thr) - time(slew_low_fall_thr)
Rise transition time: time(slew_high_rise_thr) - time(slew_low_rise_thr)
A poor choice of threshold points leads to neative delay value. Therefore a correct choice of thresholds is very important
OpenLANE allows users to make changes to environment variables on the fly. For instance, if we wish to change the pin placement from equidistant to some other style of placement we may do the following in the openLANE flow:
set ::env(FP_IO_MODE) 2
A SPICE deck includes information about the following:
- Model description
- Netlist description
- Component connectivity
- Component values
- Capacitance load
- Nodes
- Simulation type and parameters
- Libraries included
Thw sitching threshold of a CMOS inverter is the point on the transfer characteristic where Vin equals Vout (=Vm). At this point both PMOS and NOMOS are in ON state which gives rise to a leakage current
The 16-mask CMOS process consists of the following steps:
- Selection of subtrate: Secting the body/substrate material
- Creating active region for transistors: Isolation between active region pockets by SiO2 and Si3N4 deposition followed by photolithography and etching
- N-well and P-well formation: Ion implanation by Boron for P-well and by Phosphorous for N-well formation
- Formation of gate terminal: NMOS and PMOS gates formed by photolithography techniques
- LDD (lightly doped drain) formation: LDD formed to prevent hot electron effect
- Source & drain formation: Screen oxide added to avoid channelling during implants followed by Aresenic implantation and annealing
- Local interconnect formation: Removal of screen oxide by HF etching. Deposition of Ti for low resistant contacts
- Higher level metal formation: CMP for planarization followed by TiN and Tungsten deposition. Top SiN layer for chip protection
The Magic layout of a CMOS inverter will be used so as to intergate the inverter with the picorv32a design. To do this, inverter magic file is sourced from vsdstdcelldesign by cloning it within the openlane_working_dir/openlane directory as follows:
git clone https://github.com/nickson-jose/vsdstdcelldesign
This creates a vsdstdcelldesign named folder in the openlane directory. The repo's contents after cloning appear as follows:
To invoke magic to view the sky130_inv.mag file, the sky130A.tech file must be included in the command along with its path. To ease up the complexity of this command, the tech file can be copied from the magic folder to the vsdstdcelldesign folder.
The sky130_inv.mag file can then be invoked in Magic very easily:
magic -T sky130A.tech sky130_inv.mag &
In Sky130 the first layer is called the local interconnect layer or Locali as shown above.
To verify whether the layout is that of CMOS inverter, verification of P-diffusiona nd N-diffusion regions with Polysilicon can be observed:
Other verification steps are to check drain and source connections. The drains of both PMOS and NMOS must be connected to output port (here, Y) and the sources of both must be connected to power supply VDD (here, VPWR.
LEF or library exchange format: A format that tells us about cell boundaries, VDD and GND lines. It contains no info about the logic of circuit and is also used to protect the IP.
SPICE extraction: Within the Magic environment, following commands are used in tkcon to achieve .mag to .spice extraction:
extract all
ext2spice cthresh 0 rethresh 0
ext2spice
This generates the sky130_in.spice file as shown above. This SPICE deck is edited to include pshort.lib and nshort.lib which are the PMOS and NMOS libraries respectively. In addition, the minimum grid size of inverter is measured from the magic layout and incorporated into the deck as: .option scale=0.01u. The model names in the MOSFET definitions are changed to pshort.model.0 and nshort.model.0 respectively for PMOS and NMOS. Finally voltage sources and simulation commands are defined as follows:
VDD VPWR 0 3.3V
VSS VGND 0 0
Va A VGND PUSLE(0V 3.3V 0 0.1ns 0.1 ns 2ns 4ns)
.tran 1n 20n
.control
run
.endc
.end
For simulation, ngspice is invoked in ther terminal:
ngspice sky130_inv.spice
The output "y" is to be plotted with "time" and swept over the input "a":
plot y vs time a
The waveform obtained is as shown:
The spikes in the output at switching points is due to low capacitance loads. This can be taken care of by editing the spice deck to increase the load capacitance value.
Four timing parameters are used to characterize the inverter standard cell:
- Rise transition: Time taken for the output to rise from 20% of max value to 80% of max value
- Fall transition- Time taken for the output to fall from 80% of max value to 20% of max value
- Cell rise delay = time(50% output rise) - time(50% input fall)
- Cell fall delay = time(50% output fall) - time(50% input rise)
The above timing parameters can be computed by noting down various values from the ngspice waveform.
Rise transition = (2.23843 - 2.17935) = 59.08ps
Fall transition = (4.09291 - 4.05004) = 42.87ps
Cell rise delay = (2.20636 - 2.15) = 56.36ps
Cell fall delay = (4.07479 - 4.05) = 24.79ps
The technology file is a setup file that declares layer types, colors, patterns, electrical connectivity, DRC, device extraction rules and rules to read LEF and DEF files. Magic layouts can be sourced from opencircuitdesign.com using the command:
wget http://opencircuitdesign.com/open_pdks/archive/drc_tests.tgz
tar xfz drc_tests.tgz
The .magicrc loads the tech file required by the user. Since this file sets up the tech file, sky130.tech need not be mentioned in the command used to invoke Magic. Hecen Magic can be invoked more conveniently now:
magic -d XR
To analyse DRC errors, magic is invoked and the met3.mag file is opened either from the software as file-> open-> met3.mag or by running command in tkcon as magic -d XR met3. DRC errors can be found by selecting a component and typing: drc why in tkcon.
met3.6 is the name of a DRC rule. The descriptions of DRC rules can be found in the SKY130 PDK’s documentation
To check for vias in the metal3 layer, make a rectangluar selection in an empty space and paint it with the m3contact color from the color palette by clicking middle mouse button. The vias can be viewed by: cif see VIA2
In this fashion, one can search for DRC errors, read up their descriptions and resolve them by editing the technology file.
A requirement for ports as specified in tracks.info is that they should be at intersection of horizontal and vertical tracks. The CMOS Inverter ports A and Y are on li1 layer. It needs to be ensured that they're on the intersection of horizontal and vertical tracks. We access the tracks.info file for the pitch and direction information:
To ensure that ports lie on the intersection point, the grid spacing in Magic (tkcon) must be changed to the li1 X and li1 Y values. Convergence of grid and tracks can be achieved using the following command:
grid 0.46um 0.34um 0.23um 0.17um
Before the CMOS Inverter standard cell LEF is extracted, the purpose of ports must be defined: Select port A in magic:
port class input
port use signal
Select Y area
port class output
port class signal
Select VPWR area
port class inout
port use power
Select VGND area
port class inout
port use ground
LEF extraction can be carried out in tkcon as follows:
lef write
This generates sky130_vsdinv.lef file.
In order to include the new standard cell in the synthesis, copy the sky130_vsdinv.lef file to the designs/picorv32a/src directory
Since abc maps the standard cell to a library abc there must be a library that defines the CMOS inverter. The sky130_fd_sc_hd_typical.lib file from vsdstdcelldesign/libs directory needs to be copied to the designs/picorv32a/src directory (Note: the slow and fast library files may also be copied).
Next, config.tcl must be modified:
set ::env(LIB_SYNTH) "$::env(OPENLANE_ROOT)/designs/picorv32a/src/sky130/sky130_fd_sc_hd__typical.lib"
set ::env(LIB_SLOWEST) "$::env(OPENLANE_ROOT)/designs/picorv32a/src/sky130/sky130_fd_sc_hd__slow.lib"
set ::env(LIB_FASTEST) "$::env(OPENLANE_ROOT)/designs/picorv32a/src/sky130/sky130_fd_sc_hd__fast.lib"
set ::env(LIB_TYPICAL) "$::env(OPENLANE_ROOT)/designs/picorv32a/src/sky130/sky130_fd_sc_hd__typical.lib"
set ::env(EXTRA_LEFS) [glob $::env(OPENLANE_ROOT)/designs/$::env(DESIGN_NAME)/src/*.lef]
In order to integrate the standard cell in the OpenLANE flow, invoke openLANE as usual and carry out following steps:
prep -design picorv32a -tag 02-07_07-56 -overwrite
set lefs [glob $::env(DESIGN_DIR)/src/*.lef]
add_lefs -src $lefs
run_synthesis
During the synthesis run, several instances of the sky130_vsdinv cell can be observed:
Next floorplan is run, followed by placement:
init_floorplan
run_placement
To check the layout invoke magic from the results/placement directory:
magic -T /home/aastha/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.placement.def
Since the custom standard cell has been plugged into the openLANE flow, it would be visible in the layout:
Timing analysis is carried out outside the openLANE flow using OpenSTA tool. For this, a new file pre_sta.conf is created. This file would be reqiured to carry out the STA analysis. Invoke OpenSTA outside the openLANE flow as follows:
sta pre_sta.conf
Since clock tree synthesis has not been performed yet, the analysis is with respect to ideal clocks and only setup time slack is taken into consideration. The slcak value is the difference between data required time and data arrival time. The worst slack value must be greater than or equal to zero. If a negative slack is obtained, following steps may be followed:
- Change synthesis strategy, synthesis buffering and synthesis sizing values
- Review maximum fanout of cells and replace cells with high fanout
The purpose of building a clock tree is enable the clock input to reach every element and to ensure a zero clock skew. H-tree is a common methodology followed in CTS.
Before attempting a CTS run in TritonCTS tool, if the slack was attempted to be reduced in previous run, the netlist may have gotten modified by cell replacement techniques. Therefore, the verilog file needs to be modified using the write_verilog command. Then, the synthesis, floorplan and placement is run again. To run CTS use the below command:
run_cts
The CTS run adds clock buffers in therefore buffer delays come into picture and our analysis from here on deals with real clocks. Setup and hold time slacks may now be analysed in the post-CTS STA anlysis in OpenROAD within the openLANE flow:
openroad
write_db pico_cts.db
read_db pico_cts.db
read_verilog /openLANE_flow/designs/picorv32a/runs/03-07_11-25/results/synthesis/picorv32a.synthesis_cts.v
read_liberty $::env(LIB_SYNTH_COMPLETE)
link_design picorv32a
read_sdc /openLANE_flow/designs/picorv32a/src/my_base.sdc
set_propagated_clock (all_clocks)
report_checks -path_delay min_max -format full_clock_expanded -digits 4
Slack at the end of STA for typical corner:
One may also check how the timing gets affected if clock buffers are replaced. Below, clkbuf_1 was replaced:
Unlike the general ASIC flow, Power Distribution Network generation is not a part of floorplan run in OpenLANE. PDN must be generated after CTS and post-CTS STA analyses:
gen_pdn
We can confirm the success of PDN by checking the current def environment variable: echo $::env(CURRENT_DEF)
OpenLANE uses the TritonRoute tool for routing. There are 2 stages of routing:
- Global routing: Routing region is divided into rectangle grids which are represented as course 3D routes (Fastroute tool)
- Detailed routing: Finer grids and routing guides used to implement physical wiring (TritonRoute tool)
Features of TritonRoute:
- Honouring pre-processed route guides
- Assumes that each net satisfies inter guide connectivity
- Uses MILP based panel routing scheme
- Intra-layer parallel and inter-layer sequential routing framework
Running routing step in TritonRoute as part of openLANE flow:
run_routing
Routing typically uses up a lot of memory:
At the end of routing, one may see a few DRC violations. In such cases, better routing stratgies may be employed, however, this compromises on time and memory. Once routing is completed, parasitic resistances and capacitances associated with routes come into picture. These parasitics can be extracted into a SPEF file. In newer openLANE versions, SPEF extraction is a part of routing run. Following this, post-route STA may be carried out.
- In the new version, FP_CORE_UTIL, FP_CORE_VMETAL and FP_CORE_HMETAL environment variables are missing in
ioPlacer.logandconfig.tcl. They need to be included inconfig.tclfile. run_floorplanfails after the STA analysis in the new version. An alternate command can be used:init_floorplan- SPEF extraction need not be externally performed in the new version. It has been integrated into the OpenLANE flow
Note: In the new version following commands may be used for an error-free flow:
init_floorplan
place_io
global_placement_or
detailed_placement
tap_decap_or
detailed_placement
gen_pdn
run_routing
- Design of custom standard cells such as NAND, OR, clock buffers and integrating them in the openLANE flow.
- Detailed IP characterization for all corner models