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Upstream QuickLogic k6n10f flow #4045

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merged 39 commits into from
Dec 4, 2023
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@povik povik commented Nov 27, 2023

  • Look into libmap-based inference not setting the right attributes for TDP36K per-configuration renaming in QuickLogic’s master
  • Sort out the licensing issue
  • create a draft PR from Martin's branch
  • Add the tests for the base arch cells
  • Add small simulation tests for memory
    • for expected code patterns, check they infer
    • and simulation check that they work for some selected addresses
  • Add small simulation tests for DSP
    • for expected code patterns, check they infer
    • and simulation check that they work for some selected values

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povik commented Nov 27, 2023

  • check this includes changes to infer memories with initialization

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povik commented Nov 29, 2023

(I will do one final rebase with squashing of fixups when we move this PR away from draft, I want the addition of the license header be there in the commit that checked in the file.)

nakengelhardt and others added 27 commits December 4, 2023 15:52
(Copied from QuickLogic Yosys plugin repo)
Clean up the code up to Yosys standards. Drop detection of
QL_DSP2_MULTADD in io_regs since those cells can't be inferred with
the current flow anyway.
Use python script to generate tests for both SDP and TDP across multiple sizes of RAM.
Adds sync_ram_sdp_(wwr|wrr) to common blockram.v for double width write and double width read respectively.
Adds `double_sync_ram_sdp` to `common/blockram.v`, providing a test for two disjoint memories.
Refactor python blockram template to take a list of params to support the above.
Also change the smaller single TDP36K tests to also test `port_a_width` value.
Also both use the same named parameters for better mirroring.
KrystalDelusion and others added 12 commits December 4, 2023 15:52
Also limited to 16 tests per file to allow parallelism.
Previous tests are converted to new test format with no sim test steps.
Adds TDP submodule to generator.
Adds shorthand expected signal to testbench (mostly to make it easier when I look at the vcd dump to figure out what I did wrong in tests).
Expected values are now stored in full precision rather than truncating to the same value as the input.
i.e. 0x5a5a5a5a will truncate to 0x5a5a for write data but will remain 0x5a5a5a5a for expected read.
Renamed python script so that it sits next to the testbench file when alphabetically sorted.
Reverted `MAX_WIDTH` to full precision for truncation testing.
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povik commented Dec 4, 2023

Force pushed with rebase and squashing of fixup commits

@povik povik marked this pull request as ready for review December 4, 2023 14:54
@mmicko mmicko merged commit 8738143 into YosysHQ:master Dec 4, 2023
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povik commented Dec 5, 2023

@whitequark Let me look into it.

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povik commented Dec 5, 2023

@whitequark As a sidenote, what would it take to have the YoWASP build in the mainline CI?

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@povik You can add this script into whichever CI system YosysHQ is currently using (I haven't kept track of that for a while):

WASI_SDK=wasi-sdk-19.0
WASI_SDK_URL=https://github.com/WebAssembly/wasi-sdk/releases/download/wasi-sdk-19/wasi-sdk-19.0-linux.tar.gz
if ! [ -d ${WASI_SDK} ]; then curl -L ${WASI_SDK_URL} | tar xzf -; fi

cat Makefile.conf <<END
export PATH := $(pwd)/${WASI_SDK}/bin:${PATH}
WASI_SYSROOT := $(pwd)/${WASI_SDK}/share/wasi-sysroot

CONFIG := wasi
PREFIX := /

ENABLE_TCL := 0
ENABLE_READLINE := 0
ENABLE_PLUGINS := 0
ENABLE_ZLIB := 0
END

make CXX=clang

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povik commented Dec 5, 2023

@mmicko Look above. Possibly something we could add to the Jenkins CI to run on the master at least, not necessarily on every PR.

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FWIW, The WASI build without LTO (which is used with YoWASP but not in the script I gave you) should be fairly lightweight.

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mmicko commented Dec 5, 2023

Sure. Will take care of it. @whitequark thanks for the script

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Thanks @mmicko!

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5 participants