Merge pull request #4045 from povik/upstream-ql-k6n10f

Upstream QuickLogic k6n10f flow
YosysHQ · Dec 4, 2023 · 8738143 · 8738143
2 parents 96fecf0 + 22cc4af
commit 8738143
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Showing 61 changed files with 98,396 additions and 139 deletions.
diff --git a/Makefile b/Makefile
@@ -880,7 +880,8 @@ endif
 	+cd tests/arch/gowin && bash run-test.sh $(SEEDOPT)
 	+cd tests/arch/intel_alm && bash run-test.sh $(SEEDOPT)
 	+cd tests/arch/nexus && bash run-test.sh $(SEEDOPT)
-	+cd tests/arch/quicklogic && bash run-test.sh $(SEEDOPT)
+	+cd tests/arch/quicklogic/pp3 && bash run-test.sh $(SEEDOPT)
+	+cd tests/arch/quicklogic/qlf_k6n10f && bash run-test.sh $(SEEDOPT)
 	+cd tests/arch/gatemate && bash run-test.sh $(SEEDOPT)
 	+cd tests/rpc && bash run-test.sh
 	+cd tests/memfile && bash run-test.sh

diff --git a/techlibs/quicklogic/.gitignore b/techlibs/quicklogic/.gitignore
@@ -0,0 +1 @@
+/*_pm.h
diff --git a/techlibs/quicklogic/Makefile.inc b/techlibs/quicklogic/Makefile.inc
@@ -1,13 +1,43 @@
+%_pm.h: passes/pmgen/pmgen.py %.pmg
+	$(P) mkdir -p pmgen && $(PYTHON_EXECUTABLE) $< -o $@ -p $(subst _pm.h,,$(notdir $@)) $(filter-out $<,$^)
+
 OBJS += techlibs/quicklogic/synth_quicklogic.o
+OBJS += techlibs/quicklogic/ql_bram_merge.o
+OBJS += techlibs/quicklogic/ql_bram_types.o
+OBJS += techlibs/quicklogic/ql_dsp_simd.o
+OBJS += techlibs/quicklogic/ql_dsp_io_regs.o
+
+# --------------------------------------
+
+OBJS += techlibs/quicklogic/ql_dsp_macc.o
+GENFILES += techlibs/quicklogic/ql_dsp_macc_pm.h
+techlibs/quicklogic/ql_dsp_macc.o: techlibs/quicklogic/ql_dsp_macc_pm.h
+$(eval $(call add_extra_objs,techlibs/quicklogic/ql_dsp_macc_pm.h))
+
+# --------------------------------------
+
+$(eval $(call add_share_file,share/quicklogic/common,techlibs/quicklogic/common/cells_sim.v))
+
+$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/ffs_map.v))
+$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/lut_map.v))
+$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/latches_map.v))
+$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/cells_map.v))
+$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/cells_sim.v))
+$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/abc9_model.v))
+$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/abc9_map.v))
+$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/abc9_unmap.v))
 
-$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_ffs_map.v))
-$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_lut_map.v))
-$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_latches_map.v))
-$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_cells_map.v))
-$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/cells_sim.v))
-$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/lut_sim.v))
-$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_cells_sim.v))
-
-$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/abc9_model.v))
-$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/abc9_map.v))
-$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/abc9_unmap.v))
+$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/arith_map.v))
+$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/libmap_brams.txt))
+$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v))
+$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/brams_map.v))
+$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/brams_sim.v))
+$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v))
+$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/cells_sim.v))
+$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/ffs_map.v))
+$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/dsp_sim.v))
+$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/dsp_map.v))
+$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/dsp_final_map.v))
+$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/TDP18K_FIFO.v))
+$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/ufifo_ctl.v))
+$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/sram1024x18_mem.v))
diff --git a/techlibs/quicklogic/cells_sim.v → techlibs/quicklogic/common/cells_sim.v b/techlibs/quicklogic/cells_sim.v → techlibs/quicklogic/common/cells_sim.v
diff --git a/techlibs/quicklogic/lut_sim.v b/techlibs/quicklogic/lut_sim.v
diff --git a/techlibs/quicklogic/abc9_map.v → techlibs/quicklogic/pp3/abc9_map.v b/techlibs/quicklogic/abc9_map.v → techlibs/quicklogic/pp3/abc9_map.v
diff --git a/techlibs/quicklogic/abc9_model.v → techlibs/quicklogic/pp3/abc9_model.v b/techlibs/quicklogic/abc9_model.v → techlibs/quicklogic/pp3/abc9_model.v
diff --git a/techlibs/quicklogic/abc9_unmap.v → techlibs/quicklogic/pp3/abc9_unmap.v b/techlibs/quicklogic/abc9_unmap.v → techlibs/quicklogic/pp3/abc9_unmap.v
diff --git a/techlibs/quicklogic/pp3_cells_map.v → techlibs/quicklogic/pp3/cells_map.v b/techlibs/quicklogic/pp3_cells_map.v → techlibs/quicklogic/pp3/cells_map.v
diff --git a/techlibs/quicklogic/pp3_cells_sim.v → techlibs/quicklogic/pp3/cells_sim.v b/techlibs/quicklogic/pp3_cells_sim.v → techlibs/quicklogic/pp3/cells_sim.v
@@ -327,3 +327,80 @@ module qlal4s3b_cell_macro (
 );
 
 endmodule
+
+(* abc9_lut=1, lib_whitebox *)
+module LUT1 (
+  output O,
+  input I0
+);
+  parameter [1:0] INIT = 0;
+  parameter EQN = "(I0)";
+
+  // These timings are for PolarPro 3E; other families will need updating.
+  specify
+    (I0 => O) = 698; // FS -> FZ
+  endspecify
+
+  assign O = I0 ? INIT[1] : INIT[0];
+endmodule
+
+//               TZ        TSL TAB
+(* abc9_lut=2, lib_whitebox *)
+module LUT2 (
+  output O,
+  input I0, I1
+);
+  parameter [3:0] INIT = 4'h0;
+  parameter EQN = "(I0)";
+
+  // These timings are for PolarPro 3E; other families will need updating.
+  specify
+    (I0 => O) = 1251; // TAB -> TZ
+    (I1 => O) = 1406; // TSL -> TZ
+  endspecify
+
+  wire [1:0] s1 = I1 ? INIT[3:2] : INIT[1:0];
+  assign O = I0 ? s1[1] : s1[0];
+endmodule
+
+(* abc9_lut=2, lib_whitebox *)
+module LUT3 (
+  output O,
+  input I0, I1, I2
+);
+  parameter [7:0] INIT = 8'h0;
+  parameter EQN = "(I0)";
+
+  // These timings are for PolarPro 3E; other families will need updating.
+  specify
+    (I0 => O) = 1251; // TAB -> TZ
+    (I1 => O) = 1406; // TSL -> TZ
+    (I2 => O) = 1699; // ('TA1', 'TA2', 'TB1', 'TB2') -> TZ
+  endspecify
+
+  wire [3:0] s2 = I2 ? INIT[7:4] : INIT[3:0];
+  wire [1:0] s1 = I1 ? s2[3:2] : s2[1:0];
+  assign O = I0 ? s1[1] : s1[0];
+endmodule
+
+(* abc9_lut=4, lib_whitebox *)
+module LUT4 (
+  output O,
+  input I0, I1, I2, I3
+);
+  parameter [15:0] INIT = 16'h0;
+  parameter EQN = "(I0)";
+
+  // These timings are for PolarPro 3E; other families will need updating.
+  specify
+    (I0 => O) = 995;  // TBS -> CZ
+    (I1 => O) = 1437; // ('TAB', 'BAB') -> CZ
+    (I2 => O) = 1593; // ('TSL', 'BSL') -> CZ
+    (I3 => O) = 1887; // ('TA1', 'TA2', 'TB1', 'TB2', 'BA1', 'BA2', 'BB1', 'BB2') -> CZ
+  endspecify
+
+  wire [7:0] s3 = I3 ? INIT[15:8] : INIT[7:0];
+  wire [3:0] s2 = I2 ? s3[7:4] : s3[3:0];
+  wire [1:0] s1 = I1 ? s2[3:2] : s2[1:0];
+  assign O = I0 ? s1[1] : s1[0];
+endmodule
diff --git a/techlibs/quicklogic/pp3_ffs_map.v → techlibs/quicklogic/pp3/ffs_map.v b/techlibs/quicklogic/pp3_ffs_map.v → techlibs/quicklogic/pp3/ffs_map.v
diff --git a/techlibs/quicklogic/pp3_latches_map.v → techlibs/quicklogic/pp3/latches_map.v b/techlibs/quicklogic/pp3_latches_map.v → techlibs/quicklogic/pp3/latches_map.v
diff --git a/techlibs/quicklogic/pp3_lut_map.v → techlibs/quicklogic/pp3/lut_map.v b/techlibs/quicklogic/pp3_lut_map.v → techlibs/quicklogic/pp3/lut_map.v