Revert "Add attributes to module instantiation"

This reverts commit 8f207ee.
YosysHQ · Dec 4, 2023 · 96fecf0 · 96fecf0
1 parent 8bd681a
commit 96fecf0
Showing 1 changed file with 0 additions and 1 deletion.
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
@@ -1980,7 +1980,6 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 		}
 
 		RTLIL::Cell *cell = module->addCell(inst_name, inst_type);
-		import_attributes(cell->attributes, inst);
 
 		if (inst->IsPrimitive() && mode_keep)
 			cell->attributes[ID::keep] = 1;