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Yosys seems to be inconsistent with the original design.
pending-verification
This issue is pending verification and/or reproduction
#4696
opened Oct 31, 2024 by
smlz123
Yosys seems to be inconsistent with the original design.
pending-verification
This issue is pending verification and/or reproduction
#4695
opened Oct 31, 2024 by
smlz123
Yosys seems to be inconsistent with the original design.
pending-verification
This issue is pending verification and/or reproduction
#4693
opened Oct 31, 2024 by
smlz123
segfault in proc_dlatch when latch is driven by conflicting drivers
bug
#4692
opened Oct 30, 2024 by
gadfort
Yosys crash: Signal `\A' with invalid width range -1 in cells_map.v"
pending-verification
This issue is pending verification and/or reproduction
#4687
opened Oct 28, 2024 by
1353369570
yosys-filterlib misformats string values
pending-verification
This issue is pending verification and/or reproduction
#4681
opened Oct 23, 2024 by
povik
'synth_intel' command,synthesis result is wrong
pending-verification
This issue is pending verification and/or reproduction
#4673
opened Oct 17, 2024 by
CL-liao
Assert
flow.wire_comb_defs[it].size() == 1
in write_cxxrtl
bug
cxxrtl
#4664
opened Oct 14, 2024 by
rroohhh
Verilog globals appended to modules instead of prepended
pending-verification
This issue is pending verification and/or reproduction
#4653
opened Oct 10, 2024 by
jmi2k
FSM pass equivalence bug
pending-verification
This issue is pending verification and/or reproduction
#4651
opened Oct 10, 2024 by
joonho3020
sta
command hangs on some designs
pending-verification
#4648
opened Oct 9, 2024 by
lukbau
write_btor: Part selects of undriven signals are lowered as separate inputs
pending-verification
This issue is pending verification and/or reproduction
#4640
opened Oct 8, 2024 by
georgerennie
Co-simulation fails for $fa cell
pending-verification
This issue is pending verification and/or reproduction
#4638
opened Oct 7, 2024 by
RCoeurjoly
tee -q -o <bad-path>
fails silently
pending-verification
#4636
opened Oct 7, 2024 by
povik
Synthesis fails on MacOS but succeeds on Linux (possibly ABC error)
pending-verification
This issue is pending verification and/or reproduction
#4618
opened Sep 29, 2024 by
agrif
VCD file parsing error in sim pass with GHDL-generated VCDs due to whitespace handling
pending-verification
This issue is pending verification and/or reproduction
#4617
opened Sep 27, 2024 by
RCoeurjoly
Yosys Synthesis Fails with std::out_of_range Error in OPT_DEMORGAN Pass
pending-verification
This issue is pending verification and/or reproduction
#4610
opened Sep 24, 2024 by
LoSyTe
Nanoxplore synthesis does not works when using abc9 flow
pending-verification
This issue is pending verification and/or reproduction
#4606
opened Sep 19, 2024 by
samhanic
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