Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Yosys seems to be inconsistent with the original design. #4695

Open
smlz123 opened this issue Oct 31, 2024 · 0 comments
Open

Yosys seems to be inconsistent with the original design. #4695

smlz123 opened this issue Oct 31, 2024 · 0 comments
Labels
pending-verification This issue is pending verification and/or reproduction

Comments

@smlz123
Copy link

smlz123 commented Oct 31, 2024

Version

0.46+135

On which OS did this happen?

ubuntu22.04

Reproduction Steps

My Verilog original design is as follows:

module top
(y, clk, wire3, wire2, wire1, wire0);
  output wire [(32'h126):(32'h0)] y;
  input wire [(1'h0):(1'h0)] clk;
  input wire signed [(4'hb):(1'h0)] wire3;
  input wire signed [(4'hc):(1'h0)] wire2;
  input wire [(2'h2):(1'h0)] wire1;
  input wire [(4'he):(1'h0)] wire0;
  wire signed [(4'hf):(1'h0)] wire8;
  reg [(5'h11):(1'h0)] reg5 = (1'h0);
   assign y = {
                 wire8,
                 (1'h0)};
assign wire8 = (wire0[(4'h8):(3'h4)] ? {"x3T4ID"} : reg5[(4'he):(2'h3)]);
endmodule

The content of the testbench file is as follows:

`include "syn_yosys.v"

module testbench  ;
  wire [(32'h126):(32'h0)] y;
  reg [(1'h0):(1'h0)] clk;
  reg signed [(4'hb):(1'h0)] wire3;
  reg signed [(4'hc):(1'h0)] wire2;
  reg [(2'h2):(1'h0)] wire1;
  reg [(4'he):(1'h0)] wire0;
  top top1 (.y(y), .clk(clk), .wire3(wire3), .wire2(wire2), .wire1(wire1), .wire0(wire0));
  initial
    begin
      clk = (1'h0);
      {wire3, wire2, wire1, wire0} = (1'h0);
      #10 {wire3, wire2, wire1, wire0} = (254'h2ebaed0bc6299c28858ee365d06dfaa0e2690b27d6175a01c377ab98263e3e8f);
      #10 {wire3, wire2, wire1, wire0} = (254'h2373dc17df544faed315c752055b5e25fff0255612bfff4a9ecf0073ba45a902);
      #10 {wire3, wire2, wire1, wire0} = (256'hfd38ef7c3a679a17102d1350b5c735b6722e2f9b3d6b8de28d54e617d5728739);
      #10 {wire3, wire2, wire1, wire0} = (253'h179d4fafd27adb17872425a9bec44b793c17ba91c6476d8222f8a481dc6d6a01);
      #10 {wire3, wire2, wire1, wire0} = (256'h92c15901c895649ce2992cfb7230648dfe2fee6320dafb2c8b55703311c8ca5c);
      #10 {wire3, wire2, wire1, wire0} = (254'h3bdf52d269939856eb57b122e7ccffffa17c129972fa2d125654afbd37ad50f8);
      #10 {wire3, wire2, wire1, wire0} = (256'hccfeadaec0f53592c7c93fdac9b0465567b01ff6e321020ad75dc4fd4d141bd1);
      #10 {wire3, wire2, wire1, wire0} = (256'heee4e46fc790d0ce6ca635c8562f9545ed0db2d761bf5b8f4c96c3ccf7d2629a);
      #10 {wire3, wire2, wire1, wire0} = (255'h65ca2a0b85c260a767e3e25b22e79bd10c709ddb91cb7402a6f8fb45c4715725);
      #10 {wire3, wire2, wire1, wire0} = (255'h56019a59810e7810a6e00d436b113842798f736aac0b5d5b45123e18d88025a9);
      #10 {wire3, wire2, wire1, wire0} = (253'h112b030afda81ac7f40d579a4f0a15c197a24f6f1dfe213283a317708c7b2cc3);
      #10 {wire3, wire2, wire1, wire0} = (256'haadf442f467fe426232f8f873a083aeb3bc51cd53ef072bac0198c82b9597737);
      #10 {wire3, wire2, wire1, wire0} = (254'h2aa2b4ad115215c7a7ea72b9eb119a54976706c280943342d8441a9a270323cb);
      #10 {wire3, wire2, wire1, wire0} = (256'hcd506de2393cf7937bf80abf2b3fd1c5d332590347cfcbaa848e07caa062178c);
      #10 {wire3, wire2, wire1, wire0} = (252'hb9c05f56d8a40958c1de347f7a3a7f5085383431472e5e40bd9166199a14277);
      #10 {wire3, wire2, wire1, wire0} = (255'h6b799d09a82835d12146eb2ff0b0ac5295d043211eb92675d93d9f30c225da89);
      #10 {wire3, wire2, wire1, wire0} = (256'hf6fa630dcc3402f7c17d5d42f5a317193141b5bb6d5cb6421c3383ee615fe21d);
      #10 {wire3, wire2, wire1, wire0} = (256'hc085005c42f89c3f931443c59f527bdcf302a69cb0049c9d44bcf58ccfec59d0);
      #10 {wire3, wire2, wire1, wire0} = (256'h814a670a73d881ca541843b8926d2c87f4067e83614b44e3589c10c9de7b7907);
      #10 {wire3, wire2, wire1, wire0} = (256'h90865987e57a88afd0473be45350811861e357a740e78dfcfc9f911765a3a391);
      #10 {wire3, wire2, wire1, wire0} = (256'hd169a4cb4fd75a8fab14c5e9d7b6fa068d20f31c9493093eed60236a725e187a);
      #10 $finish;
    end
  always
    #5 clk = (~clk);
  always
    @(posedge clk) $strobe ("%b", y);
endmodule

Commands used for synthesis:

yosys
read_verilog rtl.v
synth
write_verilog syn_yosys.v

then,you can simulate them by the above testbench,
please note that include"syn_yosys" should changed to include"rtl.v" when you simulate the rtl.v.
Looking forward to your reply.

Expected Behavior

The simulation before and after synthesis is consistent.

Actual Behavior

Inconsistent output before and after synthesis.

@smlz123 smlz123 added the pending-verification This issue is pending verification and/or reproduction label Oct 31, 2024
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
pending-verification This issue is pending verification and/or reproduction
Projects
None yet
Development

No branches or pull requests

1 participant