A modern hardware definition language and toolchain based on Python
-
Updated
Dec 16, 2024 - Python
#
hdl
Here are 656 public repositories matching this topic...
HDL libraries and projects
-
Updated
Dec 20, 2024 - Verilog
Hardware Description Languages
-
Updated
Aug 18, 2024
A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
-
Updated
Jan 8, 2022 - Python
Veryl: A Modern Hardware Description Language
-
Updated
Dec 23, 2024 - Rust
一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。
-
Updated
Sep 15, 2023 - Bluespec
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
python rtl verilog systemverilog hdl open-source-hardware pymtl hardware-generation open-source-eda multi-level-modeling cycle-level-modeling
-
Updated
Dec 9, 2024 - Python
The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
-
Updated
Dec 17, 2024 - Dart
Open source machine learning accelerators
-
Updated
Mar 24, 2024 - Scala
PlutoSDR Firmware
linux fpga sdr iio transceiver rf hdl plutosdr adalm-pluto active-learning-module plutosdr-fw plutosdr-firmware
-
Updated
Oct 15, 2024 - Shell
VeloView performs real-time visualization and easy processing of live captured 3D LiDAR data from Velodyne sensors (Alpha Prime™, Puck™, Ultra Puck™, Puck Hi-Res™, Alpha Puck™, Puck LITE™, HDL-32, HDL-64E). Runs on Windows, Linux and MacOS. This repository is a mirror of https://gitlab.kitware.com/LidarView/VeloView-Velodyne.
lidar velodyne-sensor velodyne sensor-data hdl lidar-measurements lidar-data-manipulation lidar-camera-calibration velodyne-hdl-sensors sensor-streaming
-
Updated
Sep 29, 2021 - C++
Test suite designed to check compliance with the SystemVerilog standard.
-
Updated
Dec 23, 2024 - SystemVerilog
Reviewing some online CS courses I took
javascript ruby kotlin python c java scala networking algorithms racket assembly computer-graphics logic mathematics databases programming-languages nand2tetris operating-systems hdl smlnj
-
Updated
Oct 5, 2024 - JavaScript
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
asic fpga async verification verilog synthesis icarus-verilog fifo cdc hdl verilog-hdl fifo-queue fifo-cache verilator asic-design cross-clock-domain
-
Updated
Apr 30, 2024 - Verilog
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
python toolchain documentation fpga sphinx primitives verilog synthesis lattice hdl xilinx-fpga ice40 artix7 artix vpr kintex7 architecture-definitions verilog-simulator symbiflow verilog-simulations
-
Updated
Dec 22, 2024 - Jupyter Notebook
Improve this page
Add a description, image, and links to the hdl topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the hdl topic, visit your repo's landing page and select "manage topics."