Skip to content
@chipsalliance

CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems

CHIPS Alliance Logo

🔗 chipsalliance.org | 📫 info@chipsalliance.org

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.


The CHIPS Alliance hosts multiple open source Projects, which are Workgroups.

Popular repositories Loading

  1. chisel chisel Public

    Chisel: A Modern Hardware Design Language

    Scala 4.3k 623

  2. rocket-chip rocket-chip Public

    Rocket Chip Generator

    Scala 3.4k 1.2k

  3. verible verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

    C++ 1.5k 234

  4. riscv-dv riscv-dv Public

    Random instruction generator for RISC-V processor verification

    Python 1.1k 337

  5. Cores-VeeR-EH1 Cores-VeeR-EH1 Public

    VeeR EH1 core

    SystemVerilog 873 227

  6. firrtl firrtl Public archive

    Flexible Intermediate Representation for RTL

    Scala 740 180

Repositories

Showing 10 of 111 repositories
  • caliptra-ss Public

    HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

    SystemVerilog 15 Apache-2.0 10 42 7 Updated Apr 27, 2025
  • t1 Public

    The highest performace Cray-like RISC-V Vector in the world.

    Scala 265 Apache-2.0 34 14 22 Updated Apr 27, 2025
  • i3c-core Public
    SystemVerilog 24 Apache-2.0 6 5 0 Updated Apr 27, 2025
  • adams-bridge Public

    Post-Quantum Cryptography IP Core (Crystals-Dilithium)

    SystemVerilog 23 Apache-2.0 5 19 5 Updated Apr 27, 2025
  • sv-tests-results Public

    Output of the sv-tests runs.

    HTML 7 3 0 0 Updated Apr 27, 2025
  • caliptra-mcu-sw Public

    Caliptra MCU Software

    Rust 13 Apache-2.0 4 15 3 Updated Apr 27, 2025
  • verilator Public Forked from verilator/verilator

    Verilator open-source SystemVerilog simulator and lint system

    C++ 39 LGPL-3.0 664 0 0 Updated Apr 26, 2025
  • caliptra-sw Public

    Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

    Rust 111 Apache-2.0 55 134 57 Updated Apr 27, 2025
  • Cores-VeeR-EL2 Public

    VeeR EL2 Core

    SystemVerilog 274 Apache-2.0 82 19 1 Updated Apr 26, 2025
  • chisel Public

    Chisel: A Modern Hardware Design Language

    Scala 4,252 Apache-2.0 623 330 (1 issue needs help) 147 Updated Apr 26, 2025