CHIPS Alliance

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109 repositories

adams-bridge
Public
Post-Quantum Cryptography IP Core (Crystals-Dilithium)
cryptography digital-signature lattice pqc ml-dsa-87
SystemVerilog
•
Apache License 2.0
•1•8•0•3•Updated Oct 31, 2024Oct 31, 2024
rocket-uncore
Public
Scala
•0•6•0•3•Updated Oct 31, 2024Oct 31, 2024
t1
Public
Scala
•
Apache License 2.0
•23•116•16•23•Updated Oct 31, 2024Oct 31, 2024
sv-tests-results
Public
Output of the sv-tests runs.
HTML
•1•5•0•0•Updated Oct 31, 2024Oct 31, 2024
sv-tests
Public
Test suite designed to check compliance with the SystemVerilog standard.
rtl verilog systemverilog hdl compliance-testing symbiflow
SystemVerilog
•
ISC License
•75•292•45•21•Updated Oct 30, 2024Oct 30, 2024
caliptra-rtl
Public
HW Design Collateral for Caliptra RoT IP
SystemVerilog
•
Apache License 2.0
•36•75•70•10•Updated Oct 30, 2024Oct 30, 2024
caliptra-ss
Public
HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.
security rot ocp root-of-trust caliptra opencomputeproject
SystemVerilog
•
Apache License 2.0
•2•7•11•2•Updated Oct 30, 2024Oct 30, 2024
rocket-chip
Public
Rocket Chip Generator
chisel scala rocket-chip chip-generator riscv rtl
Scala
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Other
•1.1k•3.2k•227•61•Updated Oct 30, 2024Oct 30, 2024
caliptra-sw
Public
Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test
Rust
•
Apache License 2.0
•43•95•99•58•Updated Oct 30, 2024Oct 30, 2024
Caliptra
Public
Caliptra IP and firmware for integrated Root of Trust block
Apache License 2.0
•33•229•17•1•Updated Oct 30, 2024Oct 30, 2024
i3c-core
Public
SystemVerilog
•
Apache License 2.0
•3•6•1•1•Updated Oct 30, 2024Oct 30, 2024
chisel-nix
Public
Nix template for the chisel-based industrial designing flows.
Nix
•1•28•0•1•Updated Oct 30, 2024Oct 30, 2024
systolic
Public
A matrix multiplication implementation via systolic array
Scala
•0•1•0•0•Updated Oct 30, 2024Oct 30, 2024
Cores-VeeR-EL2
Public
VeeR EL2 Core
fpga processor riscv rtl risc-v open-source-hardware fusesoc verilator riscv32 western-digital
SystemVerilog
•
Apache License 2.0
•75•250•21•8•Updated Oct 30, 2024Oct 30, 2024
synlig
Public
SystemVerilog support for Yosys
Verilog
•
Apache License 2.0
•21•165•65•10•Updated Oct 30, 2024Oct 30, 2024
synlig-logs
Public
SystemVerilog
•0•0•0•0•Updated Oct 30, 2024Oct 30, 2024
chisel
Public
Chisel: A Modern Hardware Design Language
chip-generator chisel rtl chisel3 firrtl scala verilog
Scala
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Apache License 2.0
•594•4k•312•166•Updated Oct 29, 2024Oct 29, 2024
firrtl-spec
Public
The specification for the FIRRTL language
TeX
•28•45•22•18•Updated Oct 29, 2024Oct 29, 2024
rvdecoderdb
Public
The Scala parser to parse riscv/riscv-opcodes generate
Scala
•0•9•0•1•Updated Oct 28, 2024Oct 28, 2024
chips-alliance-website
Public
SCSS
•
MIT License
•3•3•9•8•Updated Oct 24, 2024Oct 24, 2024
verible-linter-action
Public
Automatic SystemVerilog linting in github actions with the help of Verible
Python
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Apache License 2.0
•13•27•2•0•Updated Oct 23, 2024Oct 23, 2024
riscv-vector-tests
Public
Unit tests generator for RVV 1.0
generator spike riscv testsuite rvv
Go
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Apache License 2.0
•19•58•3•1•Updated Oct 19, 2024Oct 19, 2024
caliptra-dpe
Public
High level module that implements DPE and defines high-level traits that are used to communicate with the crypto peripherals and PCRs
Rust
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Apache License 2.0
•22•16•12•6•Updated Oct 18, 2024Oct 18, 2024
verible
Public
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
productivity analysis style-linter language-server-protocol syntax-tree lexer yacc systemverilog hacktoberfest lsp-server
C++
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Other
•206•1.4k•470•24•Updated Oct 16, 2024Oct 16, 2024
f4pga
Public
FOSS Flow For FPGA
documentation sphinx symbiflow
Python
•
Apache License 2.0
•48•357•13•13•Updated Oct 15, 2024Oct 15, 2024
chisel-interface
Public
The 'missing header' for Chisel
Scala
•1•16•0•0•Updated Oct 12, 2024Oct 12, 2024
homebrew-verible
Public
Ruby
•
Apache License 2.0
•8•16•0•1•Updated Oct 8, 2024Oct 8, 2024
verilator
Public
Verilator open-source SystemVerilog simulator and lint system
C++
•
GNU Lesser General Public License v3.0
•606•34•0•1•Updated Oct 7, 2024Oct 7, 2024
Surelog
Public
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
parser linter preprocessor antlr verilog python-api systemverilog uvm elaboration vpi
C++
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Apache License 2.0
•68•362•51•0•Updated Oct 7, 2024Oct 7, 2024
UHDM
Public
Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
vpi-api serialization listener systemverilog ieee-standard vpi-interface
C++
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Apache License 2.0
•40•198•15•0•Updated Oct 7, 2024Oct 7, 2024