docs/building-examples: add linux_litex_demo and litex_sata_demo

Signed-off-by: Unai Martinez-Corral <[email protected]>
chipsalliance · Sep 10, 2022 · e626c29 · e626c29
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diff --git a/docs/building-examples.rst b/docs/building-examples.rst
@@ -77,11 +77,12 @@ Then, follow the guidelines for each example:
 .. toctree::
 
    xc7/counter_test
-   xc7/picosoc_demo
-   xc7/litex_demo
    xc7/timer
    xc7/pulse_width_led
-
+   xc7/picosoc_demo
+   xc7/litex_demo
+   xc7/linux_litex_demo
+   xc7/litex_sata_demo
 
 QuickLogic EOS S3
 =================

diff --git a/docs/xc7/linux_litex_demo.rst b/docs/xc7/linux_litex_demo.rst
@@ -0,0 +1,2 @@
+.. jinja:: xc7_linux_litex_demo
+   :file: templates/example.jinja
diff --git a/docs/xc7/litex_sata_demo.rst b/docs/xc7/litex_sata_demo.rst
@@ -0,0 +1,2 @@
+.. jinja:: xc7_litex_sata_demo
+   :file: templates/example.jinja
diff --git a/xc7/litex_sata_demo/README.rst b/xc7/litex_sata_demo/README.rst
@@ -23,16 +23,12 @@ At completion, the bitstreams are located in the build directory:
 
 To generate the source files for this test, the following packages were used:
 
-===========================================================  ========================================
-Repo URL                                                     SHA
-===========================================================  ========================================
-`LiteX <https://github.com/enjoy-digital/litex>`_            95b310ee0f0d9e78e00eb32b71324b25265da4f4
-`LiteSATA <https://github.com/enjoy-digital/litesata>`_      fae9f8d5b7b6d4c6a0a93b496bd15db5201d14f7
-`LiteDRAM <https://github.com/enjoy-digital/litedram>`_      2c60861929a317af697267d6219da43d10dcf1fa
-`LiteICLink <https://github.com/enjoy-digital/liteiclink>`_  0980a7cf4ffcb0b69a84fa0343a66180408b2a91
-`LiteX Boards <https://github.com/litex-hub/litex-boards>`_  ea58ef94a784308ae024a1d201d603bc8459a590
-`migen <https://github.com/m-labs/migen>`_                   c50ecdebd0e93c90ff44ca2e13d9f55fa97947d5
-===========================================================  ========================================
+* :gh:`LiteX <enjoy-digital/litex>`~@95b310ee0f0d9e78e00eb32b71324b25265da4f4
+* :gh:`LiteSATA <enjoy-digital/litesata>`~fae9f8d5b7b6d4c6a0a93b496bd15db5201d14f7
+* :gh:`LiteDRAM <enjoy-digital/litedram>`~@2c60861929a317af697267d6219da43d10dcf1fa
+* :gh:`LiteICLink <enjoy-digital/liteiclink>`~@0980a7cf4ffcb0b69a84fa0343a66180408b2a91
+* :gh:`LiteX Boards <litex-hub/litex-boards>`~@ea58ef94a784308ae024a1d201d603bc8459a590
+* :gh:`migen <m-labs/migen>`~@c50ecdebd0e93c90ff44ca2e13d9f55fa97947d5
 
 The generated verilog design file (litesata.v) contains a couple of fixes to properly work with the Yosys+VPR flow.
 The fixes are around the GTP high speed transceivers hard blocks.
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		@@ -0,0 +1,2 @@
		.. jinja:: xc7_linux_litex_demo
		:file: templates/example.jinja
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		@@ -0,0 +1,2 @@
		.. jinja:: xc7_litex_sata_demo
		:file: templates/example.jinja