Merge pull request YosysHQ#199 from yrabbit/clk

Himbaechel. Improve dedicated clock router
yrabbit · Sep 17, 2023 · cff0cd8 · cff0cd8
2 parents 180dfef + 984885f
commit cff0cd8
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Showing 54 changed files with 201 additions and 1,133 deletions.
diff --git a/.github/workflows/chipdb.yml b/.github/workflows/chipdb.yml
@@ -279,6 +279,7 @@ jobs:
         path: dist
     - name: Set up Python
       uses: actions/setup-python@v4
+      id: pysetup
       with:
         python-version: '3.9'
     - name: Install and build
@@ -301,7 +302,7 @@ jobs:
         sudo make install
         cd ../nextpnr
         git checkout ${{ matrix.nextpnr }}
-        cmake . -DBUILD_PYTHON=OFF -DARCH="gowin;himbaechel" -DHIMBAECHEL_GOWIN_DEVICES="GW1N-1;GW1NZ-1;GW1N-4;GW1N-9;GW1N-9C;GW1NS-4;GW2A-18;GW2A-18C" -DPython3_EXECUTABLE=/opt/hostedtoolcache/Python/3.9.17/x64/bin/python
+        cmake . -DBUILD_PYTHON=OFF -DARCH="gowin;himbaechel" -DHIMBAECHEL_GOWIN_DEVICES="GW1N-1;GW1NZ-1;GW1N-4;GW1N-9;GW1N-9C;GW1NS-4;GW2A-18;GW2A-18C" -DPython3_EXECUTABLE=${{ steps.pysetup.outputs.python-path }}
         make -j$(nproc)
         sudo make install
         cd ../examples

diff --git a/apycula/chipdb.py b/apycula/chipdb.py
@@ -113,6 +113,7 @@ class Device:
     # - OSER16/IDES16
     # - ref to hclk_pips
     # - disabled blocks
+    # - BUF(G)
     extra_func: Dict[Tuple[int, int], Dict[str, Any]] = field(default_factory=dict)
 
     @property
@@ -154,6 +155,40 @@ def bank_tiles(self):
                     res.update({ bel[4:] : pos })
         return res
 
+# XXX GW1N-4 and GW1NS-4 have next data in dat['CmuxIns']:
+# 62 [11, 1, 126]
+# 63 [11, 1, 126]
+# this means that the same wire (11, 1, 126) is connected implicitly to two
+# other logical wires. Let's remember such connections.
+# If suddenly a command is given to assign an already used wire to another
+# node, then all the contents of this node are combined with the existing one,
+# and the node itself is destroyed.  only for HCLK and clock nets for now
+wire2node = {}
+def add_node(dev, node_name, wire_type, row, col, wire):
+    if (row, col, wire) not in wire2node:
+        wire2node[row, col, wire] = node_name
+        dev.nodes.setdefault(node_name, (wire_type, set()))[1].add((row, col, wire))
+    else:
+        if node_name != wire2node[row, col, wire] and node_name in dev.nodes:
+            #print(f'{node_name} -> {wire2node[row, col, wire]} share ({row}, {col}, {wire})')
+            dev.nodes[wire2node[row, col, wire]][1].update(dev.nodes[node_name][1])
+            del dev.nodes[node_name]
+
+# create bels for entry potints to the global clock nets
+def add_buf_bel(dev, row, col, wire, buf_type = 'BUFG'):
+    # clock pins
+    if not wire.startswith('CLK'):
+        return
+    extra_func = dev.extra_func.setdefault((row, col), {})
+    if 'buf' not in extra_func or buf_type not in extra_func['buf']:
+        extra_func.update({'buf': {buf_type: [wire]}})
+    else:
+        # dups not allowed for now
+        if wire in extra_func['buf'][buf_type]:
+            #print(f'extra buf dup ({row}, {col}) {buf_type}/{wire}')
+            return
+        extra_func['buf'][buf_type].append(wire)
+
 def unpad(fuses, pad=-1):
     try:
         return fuses[:fuses.index(pad)]
@@ -962,7 +997,10 @@ def fse_create_hclk_nodes(dev, device, fse, dat):
         # entries to the HCLK from logic
         for hclk_idx, row, col, wire_idx in {(i, dat['CmuxIns'][str(i - 80)][0] - 1, dat['CmuxIns'][str(i - 80)][1] - 1, dat['CmuxIns'][str(i - 80)][2]) for i in range(hclknumbers['TBDHCLK0'], hclknumbers['RBDHCLK3'] + 1)}:
             if row != -2:
-                dev.nodes.setdefault(hclknames[hclk_idx], ("HCLK", set()))[1].add((row, col, wirenames[wire_idx]))
+                add_node(dev, hclknames[hclk_idx], "HCLK", row, col, wirenames[wire_idx])
+                # XXX clock router is doing fine with HCLK w/o any buffering
+                # may be placement suffers a bit
+                #add_buf_bel(dev, row, col, wirenames[wire_idx], buf_type = 'BUFH')
 
         if 'hclk' in hclk_info[side]:
             # create HCLK cells pips
@@ -975,7 +1013,7 @@ def fse_create_hclk_nodes(dev, device, fse, dat):
                     for src in srcs.keys():
                         for pfx in _global_wire_prefixes:
                             if src.startswith(pfx):
-                                dev.nodes.setdefault(src, ('HCLK', set()))[1].add((row, col, src))
+                                add_node(dev, src, "HCLK", row, col, src)
                 # strange GW1N-9C input-input aliases
                 for i in {0, 2}:
                     dev.nodes.setdefault(f'X{col}Y{row}/HCLK9-{i}', ('HCLK', {(row, col, f'HCLK_IN{i}')}))[1].add((row, col, f'HCLK_9IN{i}'))
@@ -1249,19 +1287,20 @@ def fse_create_clocks(dev, device, dat, fse):
     # find center muxes
     for clk_idx, row, col, wire_idx in {(i, dat['CmuxIns'][str(i - 80)][0] - 1, dat['CmuxIns'][str(i - 80)][1] - 1, dat['CmuxIns'][str(i - 80)][2]) for i in range(clknumbers['PCLKT0'], clknumbers['PCLKR1'] + 1)}:
         if row != -2:
-            dev.nodes.setdefault(clknames[clk_idx], ("GLOBAL_CLK", set()))[1].add((row, col, wirenames[wire_idx]))
+            add_node(dev, clknames[clk_idx], "GLOBAL_CLK", row, col, wirenames[wire_idx])
+            add_buf_bel(dev, row, col, wirenames[wire_idx])
 
     spines = {f'SPINE{i}' for i in range(32)}
     for row, rd in enumerate(dev.grid):
         for col, rc in enumerate(rd):
             for dest, srcs in rc.pure_clock_pips.items():
                 for src in srcs.keys():
                     if src in spines and not dest.startswith('GT'):
-                        dev.nodes.setdefault(src, ("GLOBAL_CLK", set()))[1].add((row, col, src))
+                        add_node(dev, src, "GLOBAL_CLK", row, col, src)
                 if dest in spines:
-                    dev.nodes.setdefault(dest, ("GLOBAL_CLK", set()))[1].add((row, col, dest))
+                    add_node(dev, dest, "GLOBAL_CLK", row, col, dest)
                     for src in { wire for wire in srcs.keys() if wire not in {'VCC', 'VSS'}}:
-                        dev.nodes.setdefault(src, ("GLOBAL_CLK", set()))[1].add((row, col, src))
+                        add_node(dev, src, "GLOBAL_CLK", row, col, src)
     # GBx0 <- GBOx
     for spine_pair in range(4): # GB00/GB40, GB10/GB50, GB20/GB60, GB30/GB70
         tap_start = _clock_data[device]['tap_start'][0]
@@ -1428,6 +1467,46 @@ def fse_create_io16(dev, device):
               ('OSCW', 'GW2AN-18'):  ({'OSCOUT': 'Q4'}, {}),
               }
 
+# from logic to global clocks. An interesting piece of dat['CmuxIns'], it was
+# found out experimentally that this range is responsible for the wires
+# 129: 'TRBDCLK0' - 152: 'TRMDCLK1'. Again we have a shift of 80 from the wire number
+# (see create clock aliases).
+# 124-126 equal CLK0-CLK2 so these are clearly inputs to the clock system
+# (GW1N-1 data)
+# 49 [1, 11, 124]
+# 50 [1, 11, 125]
+# 51 [6, 20, 124]
+# 52 [6, 20, 125]
+# 53 [1, 10, 125]
+# 54 [6, 1, 124]
+# 55 [6, 1, 125]
+# 56 [1, 10, 124]
+# 57 [11, 11, 124]
+# 58 [11, 11, 125]
+# 59 [7, 20, 126]
+# 60 [8, 20, 126]
+# 61 [11, 10, 125]
+# 62 [7, 1, 126]
+# 63 [8, 1, 126]
+# 64 [11, 10, 124]
+# 65 [-1, -1, -1]
+# 66 [-1, -1, -1]
+# 67 [-1, -1, -1]
+# 68 [-1, -1, -1]
+# 69 [-1, -1, -1]
+# 70 [-1, -1, -1]
+# 71 [6, 10, 126]
+# 72 [6, 11, 126]
+# We don't need to worry about routing TRBDCLK0 and the family - this was
+# already done when we created pure clock pips. But what we need to do is
+# indicate that these CLKs at these coordinates are TRBDCLK0, etc. Therefore,
+# we create Himbaechel nodes.
+def fse_create_logic2clk(dev, device, dat):
+    for clkwire_idx, row, col, wire_idx in {(i, dat['CmuxIns'][str(i - 80)][0] - 1, dat['CmuxIns'][str(i - 80)][1] - 1, dat['CmuxIns'][str(i - 80)][2]) for i in range(clknumbers['TRBDCLK0'], clknumbers['TRMDCLK1'] + 1)}:
+        if row != -2:
+            add_node(dev, clknames[clkwire_idx], "GLOBAL_CLK", row, col, wirenames[wire_idx])
+            add_buf_bel(dev, row, col, wirenames[wire_idx])
+
 def fse_create_osc(dev, device, fse):
     for row, rd in enumerate(dev.grid):
         for col, rc in enumerate(rd):
@@ -1503,6 +1582,7 @@ def from_fse(device, fse, dat):
     fse_create_io16(dev, device)
     fse_create_osc(dev, device, fse)
     fse_create_gsr(dev, device)
+    fse_create_logic2clk(dev, device, dat)
     disable_plls(dev, device)
     sync_extra_func(dev)
     return dev

diff --git a/apycula/gowin_pack.py b/apycula/gowin_pack.py
@@ -82,7 +82,7 @@ def extra_pll_bels(cell, row, col, num, cellname):
 def get_bels(data):
     later = []
     if is_himbaechel:
-        belre = re.compile(r"X(\d+)Y(\d+)/(?:GSR|LUT|DFF|IOB|MUX|ALU|ODDR|OSC[ZFHWO]?|BUFS|RAM16SDP4|RAM16SDP2|RAM16SDP1|PLL|IOLOGIC)(\w*)")
+        belre = re.compile(r"X(\d+)Y(\d+)/(?:GSR|LUT|DFF|IOB|MUX|ALU|ODDR|OSC[ZFHWO]?|BUF[GS]|RAM16SDP4|RAM16SDP2|RAM16SDP1|PLL|IOLOGIC)(\w*)")
     else:
         belre = re.compile(r"R(\d+)C(\d+)_(?:GSR|SLICE|IOB|MUX2_LUT5|MUX2_LUT6|MUX2_LUT7|MUX2_LUT8|ODDR|OSC[ZFHWO]?|BUFS|RAMW|rPLL|PLLVR|IOLOGIC)(\w*)")
 
@@ -572,7 +572,7 @@ def __init__(self, row, col, idx, attrs, flags, connections):
         'TBUF': {'ODMUX_1': 'UNKNOWN', 'PULLMODE': 'UP', 'SLEWRATE': 'FAST',
                  'DRIVE': '8', 'HYSTERESIS': 'NONE', 'CLAMP': 'OFF', 'DIFFRESISTOR': 'OFF',
                  'SINGLERESISTOR': 'OFF', 'VCCIO': '1.8', 'LVDS_OUT': 'OFF', 'DDR_DYNTERM': 'NA',
-                 'TO': 'INV', 'PERSISTENT': 'OFF', 'ODMUX': 'TRIMUX'},
+                 'TO': 'INV', 'PERSISTENT': 'OFF', 'ODMUX': 'TRIMUX', 'OPENDRAIN': 'OFF'},
         'IOBUF': {'ODMUX_1': 'UNKNOWN', 'PULLMODE': 'UP', 'SLEWRATE': 'FAST',
                  'DRIVE': '8', 'HYSTERESIS': 'NONE', 'CLAMP': 'OFF', 'DIFFRESISTOR': 'OFF',
                  'SINGLERESISTOR': 'OFF', 'VCCIO': '1.8', 'LVDS_OUT': 'OFF', 'DDR_DYNTERM': 'NA',
@@ -700,6 +700,8 @@ def place(db, tilemap, bels, cst, args):
                 bits2zero.update(tiledata.bels[f'BUFS{num}'].flags[fuses])
             for r, c in bits2zero:
                 tile[r][c] = 0
+        elif typ.startswith("BUFG"):
+            continue
 
         elif typ in {'OSC', 'OSCZ', 'OSCF', 'OSCH', 'OSCW', 'OSCO'}:
             # XXX turn on (GW1NZ-1)

diff --git a/examples/himbaechel/Makefile.himbaechel b/examples/himbaechel/Makefile.himbaechel
@@ -1,7 +1,6 @@
 YOSYS ?= yosys
-NEXTPNR ?= nextpnr-himbaechel --uarch gowin 
+NEXTPNR ?= nextpnr-himbaechel
 
-CHIPDB_PATH ?= /usr/local/share/nextpnr/himbaechel/gowin
 HIMBAECHEL_OUT ?= ./himbaechel-out
 
 .DEFAULT_GOAL := all
@@ -144,92 +143,92 @@ clean:
 	gowin_pack -d GW2A-18C -o $@ $<
 
 %-tangnano20k.json: %-tangnano20k-synth.json tangnano20k.cst
-	$(NEXTPNR) --json $< --write $@ --chipdb ${CHIPDB_PATH}/chipdb-GW2A-18C.bin --vopt partno=GW2AR-LV18QN88C8/I7 --vopt cst=tangnano20k.cst
+	$(NEXTPNR) --json $< --write $@ --device GW2AR-LV18QN88C8/I7 --vopt family=GW2A-18C --vopt cst=tangnano20k.cst
 
-%-tangnano20k-synth.json: tangnano20k/%.v
-	$(YOSYS) -D LEDS_NR=6 -D OSC_TYPE_OSC -p "read_verilog $^; synth_gowin -json $@"
+%-tangnano20k-synth.json: %.v
+	$(YOSYS) -D LEDS_NR=6 -D OSC_TYPE_OSC -D INV_BTN=1 -p "read_verilog $^; synth_gowin -json $@"
 
-pll-nanolcd-tangnano20k-synth.json: pll/GW2A-18-dyn.vh tangnano20k/TOP.v pll-nanolcd/VGAMod.v
-	$(YOSYS) -p "read_verilog $^; synth_gowin -json $@"
+pll-nanolcd-tangnano20k-synth.json: pll/GW2A-18-dyn.vh pll-nanolcd/TOP.v pll-nanolcd/VGAMod.v
+	$(YOSYS) -D INV_BTN=1 -p "read_verilog $^; synth_gowin -json $@"
 
-attosoc-tangnano20k-synth.json: tangnano20k/attosoc.v attosoc/picorv32.v
-	$(YOSYS) -p "read_verilog $^; synth_gowin -json $@"
+attosoc-tangnano20k-synth.json: attosoc/attosoc.v attosoc/picorv32.v
+	$(YOSYS) -D INV_BTN=1 -p "read_verilog $^; synth_gowin -json $@"
 
 # ============================================================
 # TangPrimer20k
 %-primer20k.fs: %-primer20k.json
 	gowin_pack -d GW2A-18 -o $@ $<
 
 %-primer20k.json: %-primer20k-synth.json primer20k.cst
-	$(NEXTPNR) --json $< --write $@ --chipdb ${CHIPDB_PATH}/chipdb-GW2A-18.bin --vopt partno=GW2A-LV18PG256C8/I7 --vopt cst=primer20k.cst
+	$(NEXTPNR) --json $< --write $@ --device GW2A-LV18PG256C8/I7 --vopt family=GW2A-18 --vopt cst=primer20k.cst
 
 %-primer20k-synth.json: %.v
-	$(YOSYS) -D LEDS_NR=6 -D OSC_TYPE_OSC -p "read_verilog $^; synth_gowin -json $@"
+	$(YOSYS) -D LEDS_NR=6 -D OSC_TYPE_OSC -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@"
 
 pll-nanolcd-primer20k-synth.json: pll/GW2A-18-dyn.vh pll-nanolcd/TOP.v pll-nanolcd/VGAMod.v
-	$(YOSYS) -p "read_verilog $^; synth_gowin -json $@"
+	$(YOSYS) -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@"
 
 attosoc-%-synth.json: attosoc/attosoc.v attosoc/picorv32.v
-	$(YOSYS) -p "read_verilog $^; synth_gowin -json $@"
+	$(YOSYS) -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@"
 
 # ============================================================
 # Tangnano (GW1N-1)
 %-tangnano.fs: %-tangnano.json
 	gowin_pack -d GW1N-1 -o $@ $^
 
 %-tangnano.json: %-tangnano-synth.json tangnano.cst
-	$(NEXTPNR) --json $< --write $@ --chipdb ${CHIPDB_PATH}/chipdb-GW1N-1.bin --vopt partno=GW1N-LV1QN48C6/I5 --vopt cst=tangnano.cst
+	$(NEXTPNR) --json $< --write $@ --device GW1N-LV1QN48C6/I5 --vopt cst=tangnano.cst
 
 %-tangnano-synth.json: %.v
-	$(YOSYS) -D LEDS_NR=3 -D OSC_TYPE_OSCH -p "read_verilog $^; synth_gowin -json $@"
+	$(YOSYS) -D LEDS_NR=3 -D OSC_TYPE_OSCH -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@"
 
 pll-nanolcd-tangnano-synth.json: pll/GW1N-1-dyn.vh pll-nanolcd/TOP.v pll-nanolcd/VGAMod.v
-	$(YOSYS) -p "read_verilog $^; synth_gowin -noalu -json $@"
+	$(YOSYS) -D INV_BTN=0 -p "read_verilog $^; synth_gowin -noalu -json $@"
 
 # ============================================================
 # Tangnano1k (GW1NZ-1)
 %-tangnano1k.fs: %-tangnano1k.json
 	gowin_pack -d GW1NZ-1 -o $@ $^
 
 %-tangnano1k.json: %-tangnano1k-synth.json tangnano1k.cst
-	$(NEXTPNR) --json $< --write $@ --chipdb ${CHIPDB_PATH}/chipdb-GW1NZ-1.bin --vopt partno=GW1NZ-LV1QN48C6/I5 --vopt cst=tangnano1k.cst
+	$(NEXTPNR) --json $< --write $@ --device GW1NZ-LV1QN48C6/I5 --vopt cst=tangnano1k.cst
 
 %-tangnano1k-synth.json: %.v
-	$(YOSYS) -D LEDS_NR=3 -D OSC_TYPE_OSCZ -p "read_verilog $^; synth_gowin -json $@"
+	$(YOSYS) -D LEDS_NR=3 -D OSC_TYPE_OSCZ -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@"
 
 pll-nanolcd-tangnano1k.fs: pll-nanolcd-tangnano1k.json
 	gowin_pack -d GW1NZ-1 --sspi_as_gpio --mspi_as_gpio -o $@ $^
 
 pll-nanolcd-tangnano1k-synth.json: pll/GW1NZ-1-dyn.vh pll-nanolcd/TOP.v pll-nanolcd/VGAMod.v
-	$(YOSYS) -p "read_verilog $^; synth_gowin -noalu -json $@"
+	$(YOSYS) -D INV_BTN=0 -p "read_verilog $^; synth_gowin -noalu -json $@"
 
 # ============================================================
 # Tangnano4k (GW1NS-4)
 %-tangnano4k.fs: %-tangnano4k.json
 	gowin_pack -d GW1NS-4 -o $@ $^
 
 %-tangnano4k.json: %-tangnano4k-synth.json tangnano4k.cst
-	$(NEXTPNR) --json $< --write $@ --chipdb ${CHIPDB_PATH}/chipdb-GW1NS-4.bin --vopt partno=GW1NSR-LV4CQN48PC7/I6 --vopt cst=tangnano4k.cst
+	$(NEXTPNR) --json $< --write $@ --device GW1NSR-LV4CQN48PC7/I6 --vopt cst=tangnano4k.cst
 
 %-tangnano4k-synth.json: %.v
-	$(YOSYS) -D LEDS_NR=6 -D OSC_TYPE_OSCZ -p "read_verilog $^; synth_gowin -json $@"
+	$(YOSYS) -D LEDS_NR=6 -D OSC_TYPE_OSCZ -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@"
 
 blinky-pll-tangnano4k-synth.json: pll/GW1NS-4-dyn.vh blinky-pll-vr.v
-	$(YOSYS) -D LEDS_NR=6 -p "read_verilog $^; synth_gowin -json $@"
+	$(YOSYS) -D INV_BTN=0 -D LEDS_NR=6 -p "read_verilog $^; synth_gowin -json $@"
 
 # ============================================================
 # Tangnano9k (GW1N-9C)
 %-tangnano9k.fs: %-tangnano9k.json
 	gowin_pack -d GW1N-9C -o $@ $^
 
 %-tangnano9k.json: %-tangnano9k-synth.json tangnano9k.cst
-	$(NEXTPNR) --json $< --write $@ --chipdb ${CHIPDB_PATH}/chipdb-GW1N-9C.bin --vopt partno=GW1NR-LV9QN88PC6/I5 --vopt cst=tangnano9k.cst
+	$(NEXTPNR) --json $< --write $@ --device GW1NR-LV9QN88PC6/I5 --vopt family=GW1N-9C --vopt cst=tangnano9k.cst
 
 %-tangnano9k-synth.json: %.v
-	$(YOSYS) -D LEDS_NR=6 -D OSC_TYPE_OSC -p "read_verilog $^; synth_gowin -json $@"
+	$(YOSYS) -D LEDS_NR=6 -D OSC_TYPE_OSC -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@"
 
 pll-nanolcd-tangnano9k-synth.json: pll/GW1N-9C-dyn.vh pll-nanolcd/TOP.v pll-nanolcd/VGAMod.v
-	$(YOSYS) -p "read_verilog $^; synth_gowin -json $@"
+	$(YOSYS) -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@"
 
 pll-nanolcd-tangnano9k.fs: pll-nanolcd-tangnano9k.json
 	gowin_pack -d GW1N-9C --sspi_as_gpio --mspi_as_gpio -o $@ $^
@@ -240,41 +239,41 @@ pll-nanolcd-tangnano9k.fs: pll-nanolcd-tangnano9k.json
 	gowin_pack -d GW1N-9 -o $@ $<
 
 %-szfpga.json: %-szfpga-synth.json szfpga.cst
-	$(NEXTPNR) --json $< --write $@ --chipdb ${CHIPDB_PATH}/chipdb-GW1N-9.bin --vopt partno=GW1NR-LV9LQ144PC6/I5 --vopt cst=szfpga.cst
+	$(NEXTPNR) --json $< --write $@ --device GW1NR-LV9LQ144PC6/I5 --vopt family=GW1N-9 --vopt cst=szfpga.cst
 
 %-szfpga-synth.json: %.v
-	$(YOSYS) -D LEDS_NR=4 -D OSC_TYPE_OSC -p "read_verilog $^; synth_gowin -json $@"
+	$(YOSYS) -D LEDS_NR=4 -D OSC_TYPE_OSC -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@"
 
 blinky-pll-szfpga-synth.json: pll/GW1N-9-dyn.vh blinky-pll.v
-	$(YOSYS) -D LEDS_NR=4 -p "read_verilog $^; synth_gowin -json $@"
+	$(YOSYS) -D INV_BTN=0 -D LEDS_NR=4 -p "read_verilog $^; synth_gowin -json $@"
 
 # ============================================================
 # tec0117 (GW1N-9)
 %-tec0117.fs: %-tec0117.json
 	gowin_pack -d GW1N-9 -o $@ $<
 
 %-tec0117.json: %-tec0117-synth.json tec0117.cst
-	$(NEXTPNR) --json $< --write $@ --chipdb ${CHIPDB_PATH}/chipdb-GW1N-9.bin --vopt partno=GW1NR-LV9QN88C6/I5 --vopt cst=tec0117.cst
+	$(NEXTPNR) --json $< --write $@ --device GW1NR-LV9QN88C6/I5 --vopt family=GW1N-9 --vopt cst=tec0117.cst
 
 %-tec0117-synth.json: %.v
-	$(YOSYS) -D LEDS_NR=8 -D OSC_TYPE_OSC -p "read_verilog $^; synth_gowin -json $@"
+	$(YOSYS) -D LEDS_NR=8 -D OSC_TYPE_OSC -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@"
 
 blinky-pll-tec0117-synth.json: pll/GW1N-9-dyn.vh blinky-pll.v
-	$(YOSYS) -D LEDS_NR=8 -p "read_verilog $^; synth_gowin -json $@"
+	$(YOSYS) -D INV_BTN=0 -D LEDS_NR=8 -p "read_verilog $^; synth_gowin -json $@"
 
 # ============================================================
 # runber (GW1N-4)
 %-runber.fs: %-runber.json
 	gowin_pack -d GW1N-4 -o $@ $<
 
 %-runber.json: %-runber-synth.json runber.cst
-	$(NEXTPNR) --json $< --write $@ --chipdb ${CHIPDB_PATH}/chipdb-GW1N-4.bin --vopt partno=GW1N-UV4LQ144C6/I5 --vopt cst=runber.cst
+	$(NEXTPNR) --json $< --write $@ --device GW1N-UV4LQ144C6/I5 --vopt cst=runber.cst
 
 %-runber-synth.json: %.v
-	$(YOSYS) -D LEDS_NR=8 -D OSC_TYPE_OSC -p "read_verilog $^; synth_gowin -json $@"
+	$(YOSYS) -D LEDS_NR=8 -D OSC_TYPE_OSC -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@"
 
 blinky-pll-runber-synth.json: pll/GW1N-4-dyn.vh blinky-pll.v
-	$(YOSYS) -D LEDS_NR=8 -p "read_verilog $^; synth_gowin -json $@"
+	$(YOSYS) -D INV_BTN=0 -D LEDS_NR=8 -p "read_verilog $^; synth_gowin -json $@"
 
 # ============================================================
 #  Upack

diff --git a/examples/himbaechel/blinky-oddr.v b/examples/himbaechel/blinky-oddr.v
@@ -3,11 +3,14 @@
 */
 module top (
 	input clk,
-	input key,
-	input rst,
+	input key_i,
+	input rst_i,
 	output [`LEDS_NR-1:0] led
 );
 
+wire key = key_i ^ `INV_BTN;
+wire rst = rst_i ^ `INV_BTN;
+
 reg [24:0] ctr_q;
 wire [24:0] ctr_d;