Modify CI to generate Himbaechel bases, build and test Himbaechel exa…

…mples (YosysHQ#197) * WIP not for merge just testing examples and bases Signed-off-by: YRabbit <[email protected]> * wip * wip * wip * wip * wip * wip * wip * wip * test-bins * test-bins * test-bins-upnpacked * test-bins-upnpacked * test-bins-upnpacked * no-python * Prepare to restore full fuctionality * Enable all legacy checks Signed-off-by: YRabbit <[email protected]> * reenable matrix --------- Signed-off-by: YRabbit <[email protected]> Co-authored-by: Pepijn de Vos <[email protected]>
yrabbit · Sep 2, 2023 · 180dfef · 180dfef
1 parent ee1ce5d
commit 180dfef
Showing 1 changed file with 10 additions and 3 deletions.
diff --git a/.github/workflows/chipdb.yml b/.github/workflows/chipdb.yml
@@ -301,11 +301,13 @@ jobs:
         sudo make install
         cd ../nextpnr
         git checkout ${{ matrix.nextpnr }}
-        cmake . -DARCH="gowin;himbaechel"
+        cmake . -DBUILD_PYTHON=OFF -DARCH="gowin;himbaechel" -DHIMBAECHEL_GOWIN_DEVICES="GW1N-1;GW1NZ-1;GW1N-4;GW1N-9;GW1N-9C;GW1NS-4;GW2A-18;GW2A-18C" -DPython3_EXECUTABLE=/opt/hostedtoolcache/Python/3.9.17/x64/bin/python
         make -j$(nproc)
         sudo make install
         cd ../examples
         make -j$(nproc) all
+        cd himbaechel
+        make -j$(nproc) -f Makefile.himbaechel all 
     - name: Archive artifact
       uses: actions/upload-artifact@v3
       with:
@@ -314,7 +316,12 @@ jobs:
     - name: Do sanity check
       run: |
         cd examples
-        make unpacked
+        make -j$(nproc) unpacked
         for f in *-unpacked.v; do
-          yosys -p "read_verilog $f; read_verilog -lib +/gowin/cells_sim.v; clean -purge; select -assert-any t:DFF*; select -assert-any t:LUT*; select -assert-any t:*BUF;";
+          yosys -p "read_verilog $f; read_verilog -lib +/gowin/cells_sim.v; clean -purge; select -assert-any t:DFF*; select -assert-any t:*BUF;";
+        done
+        cd himbaechel
+        make -j$(nproc) -f Makefile.himbaechel unpacked
+        for f in *-unpacked.v; do
+          yosys -p "read_verilog $f; read_verilog -lib +/gowin/cells_sim.v; clean -purge; select -assert-any t:DFF*; select -assert-any t:*BUF;";
         done