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+  <section id="hardware-software-co-design">
+<span id="co-design"></span><h1>Hardware-software co-design<a class="headerlink" href="#hardware-software-co-design" title="Link to this heading">¶</a></h1>
+<figure class="align-center" id="id1">
+<a class="reference internal image-reference" href="_images/software-hardware.png"><img alt="_images/software-hardware.png" src="_images/software-hardware.png" style="width: 100%;" /></a>
+<figcaption>
+<p><span class="caption-number">Fig. 2 </span><span class="caption-text">Summary of software-hardware co-execution solutions.</span><a class="headerlink" href="#id1" title="Link to this image">¶</a></p>
+</figcaption>
+</figure>
+<div class="admonition hint">
+<p class="admonition-title">Hint</p>
+<p>Hooking functions/instructions in binary applications:</p>
+<ul class="simple">
+<li><p><a class="reference external" href="https://github.com/dbhi/binhook">gh:dbhi/binhook</a></p></li>
+<li><p><a class="reference external" href="https://github.com/beehive-lab/mambo">gh:beehive-lab/mambo</a></p></li>
+<li><p><a class="reference external" href="https://github.com/dynamorio/dynamorio">gh:dynamorio/dynamorio</a></p></li>
+</ul>
+<p>Use cases:</p>
+<ul class="simple">
+<li><p>Running binaries with custom instructions on devices without hardware support.</p></li>
+<li><p>Replacing software routines with hardware accelerators, without modifying application sources.</p></li>
+<li><p>Switching drivers/implementations without recompiling the software application.</p>
+<ul>
+<li><p>For instance, evaluating accelerators on target boards before the RTL is ready for synthesis.</p></li>
+</ul>
+</li>
+</ul>
+</div>
+<ul class="simple">
+<li><p><a class="reference external" href="https://stnolting.github.io/neorv32/ug/#_adding_custom_hardware_modules">NEORV32 User Guide: Adding Custom Hardware Modules</a></p></li>
+<li><p><a class="reference external" href="https://stnolting.github.io/neorv32/">NEORV32 Datasheet</a></p>
+<ul>
+<li><p><a class="reference external" href="https://stnolting.github.io/neorv32/#_stream_link_interface">Stream Link Interface</a></p></li>
+<li><p><a class="reference external" href="https://stnolting.github.io/neorv32/#_custom_functions_subsystem_cfs">Custom Functions Subsystem (CFS)</a></p></li>
+</ul>
+</li>
+<li><p><a class="reference external" href="https://github.com/google/CFU-Playground">gh:google/CFU-Playground</a></p>
+<ul>
+<li><p><a class="reference external" href="https://www.youtube.com/watch?v=_1yrxrl61o4">youtube: CFU Playground: Model-specific Acceleration on FPGAs - Timothy Callahan &amp; Alan V. Green, Google</a></p></li>
+</ul>
+</li>
+</ul>
+<figure class="align-center" id="id2">
+<a class="reference internal image-reference" href="_images/vboard.png"><img alt="_images/vboard.png" src="_images/vboard.png" style="width: 100%;" /></a>
+<figcaption>
+<p><span class="caption-number">Fig. 3 </span><span class="caption-text"><a class="reference external" href="https://github.com/dbhi/vboard">gh:dbhi/vboard</a>: virtual development board for HDL design.</span><a class="headerlink" href="#id2" title="Link to this image">¶</a></p>
+</figcaption>
+</figure>
+<p>Co-execution platform options:</p>
+<ul class="simple">
+<li><p>Workstation/laptop (amd64)</p>
+<ul>
+<li><p>Native</p></li>
+<li><p>QEMU user mode</p></li>
+<li><p>QEMU system mode</p></li>
+</ul>
+</li>
+<li><p>Single Board Computer (SBC)</p></li>
+<li><p>FPGA board (PS only)</p></li>
+<li><p>FPGA board (PS and PL)</p></li>
+</ul>
+</section>
+
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+              <a href="https://github.com/umarcor/SIEAV/blob/main/site/Control.rst" class="fa fa-github"> Edit on GitHub</a>
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+
+  <section id="control-system-modelling-in-vhdl-2008">
+<span id="control"></span><h1>Control system modelling in VHDL 2008<a class="headerlink" href="#control-system-modelling-in-vhdl-2008" title="Link to this heading">¶</a></h1>
+<ul class="simple">
+<li><p>From 64-bit floating-point to custom fixed-point.</p>
+<ul>
+<li><p><a class="reference external" href="https://umarcor.github.io/osvb/notebook/fpconv">OSVB: fpconv</a>: data type exploration and visualization in arithmetic algorithms/circuits.</p></li>
+</ul>
+</li>
+<li><p>From a single process to a spatial synthesizable design.</p>
+<ul>
+<li><p>Clocking schemes.</p></li>
+</ul>
+</li>
+<li><p>Passing complex generics/parameters through <a class="reference external" href="https://hdl.github.io/awesome/items/json-for-vhdl">JSON-for-VHDL</a>.</p></li>
+<li><p>From an isolated core to a software-hardware partitioned design.</p>
+<ul>
+<li><p>Introduction to VUnit’s AXI <a class="reference external" href="http://vunit.github.io/verification_components/user_guide.html">verification components</a>.</p></li>
+<li><p>Direct cosimulation: VHDL and C/Python.</p></li>
+</ul>
+</li>
+</ul>
+<p><em>TBC</em></p>
+</section>
+
+
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