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Home-Office
FPGA-Engineer doing design and verification using VHDL, SystemVerilog, SVA and PSL.
- Dresden, Germany
- https://git.goodcleanfun.de
- @__tmeissner__
- xgcfx
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psl_with_ghdl
psl_with_ghdl PublicExamples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
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formal_hw_verification
formal_hw_verification PublicTrying to verify Verilog/VHDL designs with formal methods and tools
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vhdl_verification
vhdl_verification PublicExamples and design pattern for VHDL verification
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17 contributions in the last year
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March 2025
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