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PyMTL4.0 Release #264

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488093e
Rename basic_rtl to primitive
ptpan Aug 26, 2022
6584709
[WIP] Stream and dstruct
ptpan Aug 28, 2022
60d73b5
[WIP] StreamSrc/Sink test passing
ptpan Aug 28, 2022
5778a40
[WIP] example and stdlib unit tests passing
ptpan Aug 29, 2022
686db8c
[WIP] Remove out dated tests
ptpan Aug 29, 2022
6f12baf
Remove TestMasterCL
ptpan Aug 29, 2022
406ff8c
Add back the RTL-FL adapters
ptpan Aug 31, 2022
bed393f
Split adapter implementation into single files
ptpan Aug 31, 2022
519c711
Hold stream source when current message is None
ptpan Sep 8, 2022
25c3751
Add line_trace to I/OStreamIfc
ptpan Sep 8, 2022
b72cdea
[ProcFL] Add back ProcFL with adapters
ptpan Sep 10, 2022
3a6a375
get tests running on ProcFL
cbatten Sep 12, 2022
9834cc8
forgot to commit this update
cbatten Sep 12, 2022
4f5a8b1
add random delays to src/sink
cbatten Sep 22, 2022
a70db04
[dev] Add py module to dependency
ptpan Oct 26, 2022
6db6cee
add ordered option to stream sink
cbatten Nov 27, 2022
326559e
temporary fix to change mem msg type field to 3bits
cbatten Dec 1, 2022
37882bc
Fixing double/single underscore issue in translation
ptpan Feb 27, 2023
0e81097
Add non-blocking stream FL adapters
ptpan Mar 1, 2023
0eab5e3
Exposing stream-to-FL adapters in stdlib.stream
ptpan Mar 2, 2023
85300ff
Add line trace to stream-to-FL adapters
ptpan Mar 2, 2023
661c0bd
[mem] Add INV and FLUSH support to MemoryFL
ptpan Oct 26, 2022
86500e9
[mem] Add error message to out-of-bound accesses
ptpan Oct 27, 2022
8c961c7
[verilator] Force signals to toggle on posedge CLK
ptpan Oct 27, 2022
a27b176
[verilator] Add support for verilator 4.228
ptpan Oct 27, 2022
77e708d
[verilator] Update use of verilator variable name in C wrapper
ptpan Oct 27, 2022
cf51f50
[test] Fix segfault due to same toplevel name
ptpan Oct 27, 2022
d628f6a
[test] Temporarily disable tests in yosys backend
ptpan Nov 1, 2022
151edf5
[mem] Improve error messages for behavioral mem
ptpan Nov 22, 2022
fdaaad2
[error msg] Add error messages for double configuring a model
ptpan Nov 22, 2022
fbaa10c
src_file: defaults to filename where class is defined
ptpan Dec 8, 2022
fbb982c
[verilator] Use Verilator context in C/Python wrapper
ptpan Oct 23, 2023
6f0f52f
[import] Release line trace string at final
ptpan Oct 23, 2023
44002c1
[import] Use linker version script to avoid UNIQUE symbols
ptpan Oct 25, 2023
b034129
[import] Fix segfault on exit in import line trace test
ptpan Oct 26, 2023
e837b43
[gitignore] Ignore dist directory
ptpan Nov 2, 2023
e619c4a
[verilog] Refactor translation pass
ptpan Oct 12, 2023
e6fcf7d
[verilog] Use tempfile library to create tmp files
ptpan Oct 12, 2023
27e36b4
[verilog] Initial xdist support in translation/import
ptpan Oct 12, 2023
d4d0d6a
[xdist] Support parallel Verilog co-sim
ptpan Nov 2, 2023
777ea4d
[import] Set Verilog import to verbose
ptpan Nov 2, 2023
d9b4efa
[import] Remove optimization flags from g++ command
ptpan Nov 23, 2023
06174c3
[import] Update C++/Python wrapper to avoid unloading the shared lib
ptpan Nov 23, 2023
2ccab35
[unit-test] Use unique DUT class name to facilitate import
ptpan Nov 23, 2023
77ae1e1
[import] Fix variable reference in C++ wrapper
ptpan Nov 23, 2023
8647882
[dependency] Add fasteners to dependency
ptpan Nov 23, 2023
6b3997c
[ci] Upgrade to Verilator 5.016 in CI
ptpan Nov 23, 2023
609e454
[ci] Remove VERILATOR_ROOT var in CI script
ptpan Nov 23, 2023
2f023d5
[ci] Create symlink to Verilator include directory
ptpan Nov 23, 2023
a317ae8
[ci] Split Verilog and Yosys backend runs
ptpan Nov 23, 2023
c1e2dfb
[ci] Fix Yosys test path
ptpan Nov 23, 2023
1e97cfd
[stdlib] Set mem msg field type_ to its correct width
ptpan Nov 23, 2023
9e365e4
[ci] Fix Yosys test path
ptpan Nov 23, 2023
d573db8
[ci] Merge coverage reports between pytest runs
ptpan Dec 6, 2023
9ee08a5
[yosys] Deprecate use of yosys backend in examples/
ptpan Dec 6, 2023
0edc9a7
[err_msg] Use better message when slicing on Bitstruct signals
ptpan Dec 6, 2023
14d2282
Merge pull request #259 from pymtl/pp482-error-msg-slicing-non-bits
ptpan Dec 6, 2023
c23a673
[README] Point users to compile Verilator v5.016
ptpan Dec 6, 2023
8e546d8
[dsl] Add support for non-s args to refer to self
ptpan Dec 7, 2023
02b17d7
[dsl] Fix typo
ptpan Dec 7, 2023
0738bb7
Merge pull request #260 from pymtl/pp482-construct-self
ptpan Dec 7, 2023
0be16f7
[yosys] Deprecate yosys backend
ptpan Dec 7, 2023
512557d
[coverage] Disable couldnt-parse coverage warning
ptpan Dec 7, 2023
58ea59a
[test] Remove return values from mamba unit tests
ptpan Dec 7, 2023
7e55309
[import] Fix data type declaration for signals of different widths
ptpan Dec 7, 2023
7ce58d5
[setup] Add fasteners to dependency
ptpan Dec 7, 2023
c8e2ab5
[import] Use explicitly sized uint types for signal declaration
ptpan Dec 7, 2023
aa19bfb
[rtlir] Add visit_Constant to behavioral visitor
ptpan Dec 7, 2023
824ee65
[test] Use variable instead of int in extslice test case
ptpan Dec 7, 2023
6da7397
[test] Fix visit_Str test
ptpan Dec 7, 2023
1bf1b7d
[import] Add an import test that uses assertion
ptpan Dec 7, 2023
25c0752
[import] Implement Verilator assertion failure without aborting process
ptpan Dec 7, 2023
adc9056
[import] Fix a bug in Verilog trace of generators
ptpan Jan 29, 2024
8c04957
[test] Fix bitstruct hypothesis test
ptpan Feb 6, 2024
84621d2
[pytest] Skip yosys tests by default
ptpan Feb 6, 2024
86952f5
[ci] Add new Python versions and remove 3.6
ptpan Feb 12, 2024
6cfd5b3
[ci] Update to checkout@v4 and setup-python@v5
ptpan Feb 12, 2024
b8c71b8
Adding __len__ interface and formatting to black
KelvinChung2000 Apr 2, 2024
6cf12f8
Undo formatting
KelvinChung2000 Apr 2, 2024
22230dd
add test
KelvinChung2000 Apr 4, 2024
49bfcb1
Add new line at end of file
yo96 Apr 4, 2024
d5bf3ba
Remove trailing white spaces.
yo96 Apr 4, 2024
198430b
Merge pull request #272 from KelvinChung2000/len-interface
yo96 Apr 4, 2024
2eb57d3
Fix issue with pytest_cmdline_preparse
cbatten Apr 22, 2024
b39d505
Improve index handling in Bits and Signal classes
KelvinChung2000 Apr 30, 2024
d0bc16e
Adding test
KelvinChung2000 Apr 30, 2024
05d82ac
update ast helper
KelvinChung2000 May 1, 2024
07b3bbb
Merge pull request #275 from KelvinChung2000/improve-indexing
yo96 Jun 3, 2024
ea01547
Verilator now requires C++14
cbatten Aug 17, 2024
212f548
add VTB_OUTPUT_DELAY for vtbgen
cbatten Feb 15, 2025
5c56dba
[tbgen] use Top as top module name
cbatten Feb 15, 2025
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[verilog] Use tempfile library to create tmp files
ptpan committed Nov 23, 2023
commit e6fcf7dcc30b9d489405a37d2932b2470a9cd75a
Original file line number Diff line number Diff line change
@@ -4,7 +4,7 @@
# Author : Peitian Pan
# Date : March 12, 2019
"""Translate a PyMTL component hierarhcy into SystemVerilog source code."""
import os
import os, tempfile

from pymtl3 import MetadataKey
from pymtl3.passes.BasePass import BasePass
@@ -148,30 +148,35 @@ def traverse_hierarchy( s, m ):
filename = f"{module_name}__pickled"

output_file = filename + '.v'
temporary_file = filename + '.v.tmp'

# First write the file to a temporary file
# Create a temporary file under the current directory.
is_same = False
with open( temporary_file, 'w' ) as output:
output.write( s.translator.hierarchy.src )
output.flush()
os.fsync( output )
output.close()

# `is_same` is set if there exists a file that has the same filename as
# `output_file`, and that file is the same as the temporary file
if ( os.path.exists(output_file) ):
is_same = verilog_cmp( temporary_file, output_file )

# Rename the temporary file to the output file
os.rename( temporary_file, output_file )

# Expose some attributes about the translation process
m.set_metadata( c.is_same, is_same )
m.set_metadata( c.translator, s.translator )
m.set_metadata( c.translated, True )
m.set_metadata( c.translated_filename, output_file )
m.set_metadata( c.translated_top_module, module_name )
tmp_fd, tmp_path = tempfile.mkstemp(dir=os.curdir, text=True)

with open(tmp_path, "w+") as tmp_file:
tmp_file.write( s.translator.hierarchy.src )
tmp_file.flush()
os.fsync( tmp_file )

# `is_same` is set if there exists a file that has the same filename as
# `output_file`, and that file is the same as the temporary file.
if ( os.path.exists(output_file) ):
is_same = verilog_cmp( tmp_file, output_file )

# Rename the temporary file to the output file.
os.replace( tmp_path, output_file )

# Expose some attributes about the translation process.
m.set_metadata( c.is_same, is_same )
m.set_metadata( c.translator, s.translator )
m.set_metadata( c.translated, True )
m.set_metadata( c.translated_filename, output_file )
m.set_metadata( c.translated_top_module, module_name )

# Clean up the temporary file.
os.close( tmp_fd )
if os.path.exists( tmp_path ):
os.remove( tmp_path )

else:
for child in m.get_child_components(repr):
13 changes: 9 additions & 4 deletions pymtl3/passes/backends/verilog/util/utility.py
Original file line number Diff line number Diff line change
@@ -61,10 +61,15 @@ def get_file_hash( file_path ):
hash_inst.update(string)
return hash_inst.hexdigest()

def get_lean_verilog_file( file_path ):
with open(file_path) as fd:
file_v = [x for x in fd.readlines() if x != '\n' and not x.startswith('//')]
return file_v
def get_lean_verilog( fd ):
return [x for x in fd.readlines() if x != '\n' and not x.startswith('//')]

def get_lean_verilog_file( file_path_or_fd ):
if hasattr( file_path_or_fd, 'readlines' ):
return get_lean_verilog(file_path_or_fd)
else:
with open(file_path_or_fd) as fd:
return get_lean_verilog(fd)

def get_hash_of_lean_verilog( file_path ):
hash_inst = blake2b()