-
Notifications
You must be signed in to change notification settings - Fork 49
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
PyMTL4.0 Release #264
Open
ptpan
wants to merge
100
commits into
master
Choose a base branch
from
pymtl4.0-dev
base: master
Could not load branches
Branch not found: {{ refName }}
Loading
Could not load tags
Nothing to show
Loading
Are you sure you want to change the base?
Some commits from the old base branch may be removed from the timeline,
and old review comments may become outdated.
Open
PyMTL4.0 Release #264
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Codecov ReportAttention: Patch coverage is
Additional details and impacted files@@ Coverage Diff @@
## master #264 +/- ##
==========================================
+ Coverage 89.18% 90.27% +1.09%
==========================================
Files 330 317 -13
Lines 30440 29286 -1154
==========================================
- Hits 27147 26438 -709
+ Misses 3293 2848 -445 ☔ View full report in Codecov by Sentry. 🚀 New features to boost your workflow:
|
Adding __len__ interface
The pytest_cmdline_preparse hook is now deprecated. I think there should be a way to achieve the same effect using pytest_load_initial_conftests https://docs.pytest.org/en/7.1.x/reference/reference.html#pytest.hookspec.pytest_cmdline_preparse However, were were using this to hook to prevent *.pyc and __pycache__ files from being generated. I think it is fine for now to just go back to generating these files.
Improve index handling in Bits and Signal classes
We were using this in our generated Verilog test bench: always #(`CYCLE_TIME/2) clk = ~clk; But if CYCLE_TIME is an odd integer (say 9) this would result in integer division and round down (i.e., with a cycle time of 9 we would end up with a clock period of 8!). This doesn't matter unless we are doing back- annotated gate-level simulation _and_ we use an odd integer clock period which is why we never detected this bug before. The fix is to simply force floating point division. always #((`CYCLE_TIME*1.0)/2) clk = ~clk;
We were seeing a bug where if you ran a bunch of tests with --dump-vcd PyMTL3 would only dump the VCD for the first test, although every once and a while it would indeed dump VCD files for the every test. This seems to have something to do with the shared library. The cleanest fix seems to be to avoid hard coding the VCD file name in the generated PyMTL wrapper and instead to dynamically get the VCD file name from the metadata.
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
This PR includes changes that will be part of the PyMTL 4.0 release. Here is a list of changes included in this PR (WIP):
xdist
module