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PyMTL4.0 Release #264

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PyMTL4.0 Release #264

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@ptpan ptpan commented Jan 29, 2024

This PR includes changes that will be part of the PyMTL 4.0 release. Here is a list of changes included in this PR (WIP):

  • Support for Verilator 5.016, including Verilog import support and CI setup
  • Revamped Verilog import support to address data corruption / segfaults
  • Support for parallel pytest runs with the xdist module
  • Support for Verilator assertion

ptpan and others added 30 commits November 23, 2023 14:21
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codecov bot commented Jan 29, 2024

Codecov Report

Attention: Patch coverage is 91.29603% with 182 lines in your changes missing coverage. Please review.

Project coverage is 90.27%. Comparing base (fc7c3fa) to head (62a62e4).
Report is 3 commits behind head on master.

Files with missing lines Patch % Lines
pymtl3/stdlib/mem/MemRequesterAdapterFL.py 20.63% 50 Missing ⚠️
pymtl3/stdlib/xcel/XcelRequesterAdapterFL.py 19.60% 41 Missing ⚠️
pymtl3/stdlib/stream/OStreamEnqAdapterFL.py 28.00% 18 Missing ⚠️
pymtl3/stdlib/stream/IStreamDeqAdapterFL.py 35.00% 13 Missing ⚠️
...ends/verilog/import_/VerilogVerilatorImportPass.py 85.29% 10 Missing ⚠️
...sses/rtlir/structural/StructuralRTLIRSignalExpr.py 75.00% 6 Missing ⚠️
pymtl3/stdlib/test_utils/test_helpers.py 50.00% 5 Missing ⚠️
.../passes/backends/verilog/VerilogPlaceholderPass.py 0.00% 4 Missing ⚠️
pymtl3/stdlib/mem/MemoryFL.py 87.87% 4 Missing ⚠️
pymtl3/stdlib/stream/ifcs/ifcs.py 66.66% 4 Missing ⚠️
... and 15 more
Additional details and impacted files
@@            Coverage Diff             @@
##           master     #264      +/-   ##
==========================================
+ Coverage   89.18%   90.27%   +1.09%     
==========================================
  Files         330      317      -13     
  Lines       30440    29286    -1154     
==========================================
- Hits        27147    26438     -709     
+ Misses       3293     2848     -445     

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ptpan and others added 27 commits February 6, 2024 14:34
The pytest_cmdline_preparse hook is now deprecated. I think there should
be a way to achieve the same effect using pytest_load_initial_conftests

https://docs.pytest.org/en/7.1.x/reference/reference.html#pytest.hookspec.pytest_cmdline_preparse

However, were were using this to hook to prevent *.pyc and __pycache__
files from being generated. I think it is fine for now to just go back
to generating these files.
Improve index handling in Bits and Signal classes
We were using this in our generated Verilog test bench:

  always #(`CYCLE_TIME/2) clk = ~clk;

But if CYCLE_TIME is an odd integer (say 9) this would result in integer
division and round down (i.e., with a cycle time of 9 we would end up with
a clock period of 8!). This doesn't matter unless we are doing back-
annotated gate-level simulation _and_ we use an odd integer clock period
which is why we never detected this bug before. The fix is to simply
force floating point division.

  always #((`CYCLE_TIME*1.0)/2) clk = ~clk;
We were seeing a bug where if you ran a bunch of tests with --dump-vcd
PyMTL3 would only dump the VCD for the first test, although every once
and a while it would indeed dump VCD files for the every test. This
seems to have something to do with the shared library. The cleanest
fix seems to be to avoid hard coding the VCD file name in the generated
PyMTL wrapper and instead to dynamically get the VCD file name from
the metadata.
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4 participants