Add internal CI tests

.github/workflows/ci.yml

@@ -56,3 +56,17 @@ jobs:
           extra_args: "--rules=-interface-name-style --lint_fatal --parse_fatal --waiver_files .github/waiver.verible"
           github_token: ${{ secrets.GITHUB_TOKEN }}
           reviewdog_reporter: github-check
+  gitlab-ci:
+    runs-on: ubuntu-latest
+    steps:
+      - name: Mirror and check
+        uses: pulp-platform/pulp-actions/gitlab-ci@v2
+        # Skip on forks or pull requests from forks due to missing secrets.
+        if: >
+          github.repository == 'pulp-platform/redundancy_cells' &&
+          (github.event_name != 'pull_request' ||
+          github.event.pull_request.head.repo.full_name == github.repository)
+        with:
+          domain: iis-git.ee.ethz.ch
+          repo: github-mirror/redundancy_cells
+          token: ${{ secrets.GITLAB_TOKEN }}

.gitlab-ci.yml

@@ -0,0 +1,18 @@
+# Copyright 2022 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+
+# Author: Michael Rogenmoser <[email protected]>
+
+stages:
+  - test
+
+test:
+  variables:
+    VSIM: "questa-2023.4 vsim"
+  stage: test
+  script: ./run_tests.sh
+  artifacts:
+    paths:
+      - vcom.log
+      - vsim.log

run_tests.sh

@@ -19,8 +19,9 @@ set -e
 VSIM_LOGFILE=vsim.log
 
 bender script vsim -t test -t rtl --vlog-arg="-svinputport=compat" -t deprecated > compile.tcl
+echo "return 0" >> compile.tcl
 
-$VSIM -c -do 'source compile.tcl; quit' > vcom.log
+$VSIM -c -do 'quit -code [source compile.tcl]' > vcom.log
 
 rm -f $VSIM_LOGFILE
 
@@ -33,7 +34,7 @@ call_vsim() {
   echo "  --> $@"
   tail -7 $VSIM_LOGFILE
   echo ""
-  # grep "Errors: 0," vsim.log
+  tail -1 vsim.log | grep "Errors: 0," > /dev/null
 }
 
 call_vsim tb_tmr_voter