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Time-based Redundancy Modules #104

Time-based Redundancy Modules

Time-based Redundancy Modules #104

Re-run triggered June 28, 2024 13:00
Status Failure
Total duration 1m 55s
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ci.yml

on: pull_request
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2 errors and 11 warnings
lint-verilog
reviewdog: Too many results (annotations) in diff. You may miss some annotations due to GitHub limitation for annotation created by logging command. Please check GitHub Actions log console to see all results. Limitation: - 10 warning annotations and 10 error annotations per step - 50 annotations per job (sum of annotations from all the steps) - 50 annotations per run (separate from the job annotations, these annotations aren't created by users) Source: https://github.community/t5/GitHub-Actions/Maximum-number-of-annotations-that-can-be-created-using-GitHub/m-p/39085
lint-verilog
Process completed with exit code 1.
check-stale
Node.js 16 actions are deprecated. Please update the following actions to use Node.js 20: actions/checkout@v3, actions/setup-python@v4. For more information see: https://github.blog/changelog/2023-09-22-github-actions-transitioning-from-node-16-to-node-20/.
lint-verilog: rtl/time_redundancy/retry_end.sv#L22
[verible-verilog-lint] reported by reviewdog 🐶 Explicitly define a storage type for every parameter and localparam, (IDSize). [Style: constants] [explicit-parameter-storage-type] Raw Output: message:"Explicitly define a storage type for every parameter and localparam, (IDSize). [Style: constants] [explicit-parameter-storage-type]" location:{path:"./rtl/time_redundancy/retry_end.sv" range:{start:{line:22 column:15}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
lint-verilog: rtl/time_redundancy/time_DMR_start.sv#L112
[verible-verilog-lint] reported by reviewdog 🐶 Explicitly define a default case for every case statement or add `unique` qualifier to the case statement. [Style: case-statements] [case-missing-default] Raw Output: message:"Explicitly define a default case for every case statement or add `unique` qualifier to the case statement. [Style: case-statements] [case-missing-default]" location:{path:"./rtl/time_redundancy/time_DMR_start.sv" range:{start:{line:112 column:13}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
lint-verilog: rtl/time_redundancy/time_DMR_start.sv#L164
[verible-verilog-lint] reported by reviewdog 🐶 Explicitly define a default case for every case statement or add `unique` qualifier to the case statement. [Style: case-statements] [case-missing-default] Raw Output: message:"Explicitly define a default case for every case statement or add `unique` qualifier to the case statement. [Style: case-statements] [case-missing-default]" location:{path:"./rtl/time_redundancy/time_DMR_start.sv" range:{start:{line:164 column:13}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
lint-verilog: rtl/time_redundancy/time_TMR_start.sv#L83
[verible-verilog-lint] reported by reviewdog 🐶 Explicitly define a default case for every case statement or add `unique` qualifier to the case statement. [Style: case-statements] [case-missing-default] Raw Output: message:"Explicitly define a default case for every case statement or add `unique` qualifier to the case statement. [Style: case-statements] [case-missing-default]" location:{path:"./rtl/time_redundancy/time_TMR_start.sv" range:{start:{line:83 column:13}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
lint-verilog: rtl/time_redundancy/time_TMR_start.sv#L140
[verible-verilog-lint] reported by reviewdog 🐶 Explicitly define a default case for every case statement or add `unique` qualifier to the case statement. [Style: case-statements] [case-missing-default] Raw Output: message:"Explicitly define a default case for every case statement or add `unique` qualifier to the case statement. [Style: case-statements] [case-missing-default]" location:{path:"./rtl/time_redundancy/time_TMR_start.sv" range:{start:{line:140 column:13}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
lint-verilog: rtl/time_redundancy/rr_arb_tree_lock.sv#L179
[verible-verilog-lint] reported by reviewdog 🐶 180:35: The lines can't be continued with '\', use concatenation operator with braces [Style: forbid-line-continuations] [forbid-line-continuations] Raw Output: message:"180:35: The lines can't be continued with '\\', use concatenation operator with braces [Style: forbid-line-continuations] [forbid-line-continuations]" location:{path:"./rtl/time_redundancy/rr_arb_tree_lock.sv" range:{start:{line:179 column:28}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
lint-verilog: rtl/time_redundancy/rr_arb_tree_lock.sv#L186
[verible-verilog-lint] reported by reviewdog 🐶 187:37: The lines can't be continued with '\', use concatenation operator with braces [Style: forbid-line-continuations] [forbid-line-continuations] Raw Output: message:"187:37: The lines can't be continued with '\\', use concatenation operator with braces [Style: forbid-line-continuations] [forbid-line-continuations]" location:{path:"./rtl/time_redundancy/rr_arb_tree_lock.sv" range:{start:{line:186 column:28}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
lint-verilog: rtl/time_redundancy/time_TMR_end.sv#L181
[verible-verilog-lint] reported by reviewdog 🐶 Line length exceeds max: 100; is: 140 [Style: line-length] [line-length] Raw Output: message:"Line length exceeds max: 100; is: 140 [Style: line-length] [line-length]" location:{path:"./rtl/time_redundancy/time_TMR_end.sv" range:{start:{line:181 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
lint-verilog: rtl/time_redundancy/time_TMR_end.sv#L182
[verible-verilog-lint] reported by reviewdog 🐶 Line length exceeds max: 100; is: 135 [Style: line-length] [line-length] Raw Output: message:"Line length exceeds max: 100; is: 135 [Style: line-length] [line-length]" location:{path:"./rtl/time_redundancy/time_TMR_end.sv" range:{start:{line:182 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
lint-verilog: rtl/time_redundancy/time_TMR_end.sv#L183
[verible-verilog-lint] reported by reviewdog 🐶 Line length exceeds max: 100; is: 135 [Style: line-length] [line-length] Raw Output: message:"Line length exceeds max: 100; is: 135 [Style: line-length] [line-length]" location:{path:"./rtl/time_redundancy/time_TMR_end.sv" range:{start:{line:183 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}