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Fix Yosys #86

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4 changes: 0 additions & 4 deletions Bender.yml
Original file line number Diff line number Diff line change
Expand Up @@ -87,7 +87,3 @@ sources:
- tb/mock_uart_axi.sv
- tb/pulp_cluster_tb.sv

- target: cluster_standalone
files:
- include/pulp_interfaces.sv

Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.

`include "pulp_soc_defines.sv"
`include "pulp_cluster/pulp_soc_defines.sv"

interface XBAR_TCDM_BUS;

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File renamed without changes.
3 changes: 1 addition & 2 deletions rtl/cluster_interconnect_wrap.sv
Original file line number Diff line number Diff line change
Expand Up @@ -16,9 +16,8 @@

`include "hci_helpers.svh"

import hci_package::*;

module cluster_interconnect_wrap
import hci_package::*;
#(
parameter NB_CORES = 12,
parameter HWPE_PRESENT = 1,
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3 changes: 1 addition & 2 deletions rtl/hwpe_subsystem.sv
Original file line number Diff line number Diff line change
Expand Up @@ -15,10 +15,9 @@

`include "hci_helpers.svh"

module hwpe_subsystem
import hci_package::*;
import pulp_cluster_package::*;

module hwpe_subsystem
#(
parameter hwpe_subsystem_cfg_t HWPE_CFG = '0,
parameter int unsigned N_CORES = 8,
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4 changes: 2 additions & 2 deletions rtl/pulp_cluster.sv
Original file line number Diff line number Diff line change
Expand Up @@ -19,8 +19,8 @@

`include "axi/typedef.svh"
`include "axi/assign.svh"
`include "cluster_bus_defines.sv"
`include "pulp_interfaces.sv"
`include "pulp_cluster/cluster_bus_defines.sv"
`include "pulp_cluster/pulp_interfaces.sv"
`include "register_interface/typedef.svh"

module pulp_cluster
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2 changes: 1 addition & 1 deletion tb/pulp_cluster_tb.sv
Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@

`timescale 1ps/1ps

`include "pulp_soc_defines.sv"
`include "pulp_cluster/pulp_soc_defines.sv"
`include "axi/assign.svh"
`include "axi/typedef.svh"

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