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UCT/IB/MLX5/DC: introducing dcs_hybrid policy #10138
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65046c8
UCT/IB/MLX5/DC: introducing dcs_hybrid policy
roiedanino e2510f5
UCT/IB/MLX5/DC: reduced branches in fast path
roiedanino 9bace1e
UCT/IB/MLX5/DC: tiny - clang-format (space)
roiedanino 1796b18
UCT/IB/MLX5/DC: use iface attribute to avoid extra branches
roiedanino 8aa351f
Merge branch 'master' into hw-dcs-2
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Original file line number | Diff line number | Diff line change |
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@@ -13,7 +13,8 @@ | |
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#include "dc_mlx5.h" | ||
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#define UCT_DC_MLX5_EP_NO_DCI ((uint8_t)-1) | ||
#define UCT_DC_MLX5_EP_NO_DCI ((uint8_t)-1) | ||
#define UCT_DC_MLX5_HW_DCI_INDEX 0 | ||
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#define UCT_DC_MLX5_TXQP_DECL(_txqp, _txwq) \ | ||
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@@ -266,6 +267,19 @@ uct_dc_mlx5_iface_is_dci_shared(const uct_dc_mlx5_iface_t *iface) | |
return iface->tx.policy >= UCT_DC_TX_POLICY_SHARED_FIRST; | ||
} | ||
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static UCS_F_ALWAYS_INLINE int | ||
uct_dc_mlx5_iface_is_dcs_quota_or_hybrid(const uct_dc_mlx5_iface_t *iface) | ||
{ | ||
return UCS_BIT(iface->tx.policy) & (UCS_BIT(UCT_DC_TX_POLICY_DCS_QUOTA) | | ||
UCS_BIT(UCT_DC_TX_POLICY_DCS_HYBRID)); | ||
} | ||
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static UCS_F_ALWAYS_INLINE int | ||
uct_dc_mlx5_iface_is_hybrid(const uct_dc_mlx5_iface_t *iface) | ||
{ | ||
return iface->tx.policy == UCT_DC_TX_POLICY_DCS_HYBRID; | ||
} | ||
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static UCS_F_ALWAYS_INLINE ucs_arbiter_group_t* | ||
uct_dc_mlx5_ep_rand_arb_group(uct_dc_mlx5_iface_t *iface, uct_dc_mlx5_ep_t *ep) | ||
{ | ||
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@@ -315,18 +329,30 @@ uct_dc_mlx5_init_dci_config(uct_dc_mlx5_dci_config_t *dci_config, | |
dci_config->max_rd_atomic = max_rd_atomic; | ||
} | ||
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static UCS_F_ALWAYS_INLINE int | ||
uct_dc_mlx5_is_hw_dci(const uct_dc_mlx5_iface_t *iface, uint8_t dci) | ||
{ | ||
return dci == iface->tx.hybrid_hw_dci; | ||
} | ||
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ucs_status_t static UCS_F_ALWAYS_INLINE | ||
uct_dc_mlx5_dci_pool_init_dci(uct_dc_mlx5_iface_t *iface, uint8_t pool_index, | ||
uint8_t dci_index) | ||
{ | ||
uct_dc_mlx5_dci_pool_t *pool = &iface->tx.dci_pool[pool_index]; | ||
uct_dc_dci_t *dci = uct_dc_mlx5_iface_dci(iface, dci_index); | ||
uint8_t num_channels = 1; | ||
ucs_status_t status; | ||
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ucs_assertv(ucs_array_length(&pool->stack) < iface->tx.ndci, | ||
"stack length exceeded ndci"); | ||
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status = uct_dc_mlx5_iface_create_dci(iface, dci_index, 1); | ||
if (uct_dc_mlx5_iface_is_hw_dcs(iface) || | ||
uct_dc_mlx5_is_hw_dci(iface, dci_index)) { | ||
num_channels = iface->tx.num_dci_channels; | ||
} | ||
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status = uct_dc_mlx5_iface_create_dci(iface, dci_index, 1, num_channels); | ||
if (status != UCS_OK) { | ||
ucs_error("iface %p: failed to create dci %u at pool %u", iface, | ||
dci_index, pool_index); | ||
|
@@ -342,11 +368,19 @@ uct_dc_mlx5_dci_pool_init_dci(uct_dc_mlx5_iface_t *iface, uint8_t pool_index, | |
static UCS_F_ALWAYS_INLINE ucs_status_t | ||
uct_dc_mlx5_ep_basic_init(uct_dc_mlx5_iface_t *iface, uct_dc_mlx5_ep_t *ep) | ||
{ | ||
uct_dc_dci_t *dci; | ||
size_t dcis_array_size; | ||
uct_dc_dci_t *dci; | ||
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ucs_arbiter_group_init(&ep->arb_group); | ||
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if ((uct_dc_mlx5_iface_is_hw_dcs(iface) || | ||
uct_dc_mlx5_iface_is_hybrid(iface)) && | ||
ucs_array_is_empty(&iface->tx.dcis)) { | ||
uct_dc_mlx5_iface_resize_and_fill_dcis(iface, 1); | ||
uct_dc_mlx5_dci_pool_init_dci(iface, uct_dc_mlx5_ep_pool_index(ep), | ||
UCT_DC_MLX5_HW_DCI_INDEX); | ||
} | ||
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if (uct_dc_mlx5_iface_is_dci_rand(iface)) { | ||
/* coverity[dont_call] */ | ||
ep->dci = rand_r(&iface->tx.rand_seed) % iface->tx.ndci; | ||
|
@@ -360,22 +394,17 @@ uct_dc_mlx5_ep_basic_init(uct_dc_mlx5_iface_t *iface, uct_dc_mlx5_ep_t *ep) | |
ep->dci); | ||
} | ||
} else if (uct_dc_mlx5_iface_is_hw_dcs(iface)) { | ||
ucs_assertv(iface->tx.ndci == 1, "ndci=%u", iface->tx.ndci); | ||
if (ucs_array_is_empty(&iface->tx.dcis)) { | ||
uct_dc_mlx5_iface_resize_and_fill_dcis(iface, 1); | ||
uct_dc_mlx5_dci_pool_init_dci(iface, uct_dc_mlx5_ep_pool_index(ep), | ||
0); | ||
} | ||
ep->dci = 0; | ||
ep->dci = UCT_DC_MLX5_HW_DCI_INDEX; | ||
dci = uct_dc_mlx5_iface_dci(iface, ep->dci); | ||
ep->dci_channel_index = dci->next_channel_index++; | ||
} else { | ||
/* Hybrid or software dcs */ | ||
ep->dci = UCT_DC_MLX5_EP_NO_DCI; | ||
ep->dci_channel_index = 0; | ||
} | ||
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return uct_rc_fc_init(&ep->fc, &iface->super.super | ||
UCS_STATS_ARG(ep->super.stats)); | ||
return uct_rc_fc_init(&ep->fc, | ||
&iface->super.super UCS_STATS_ARG(ep->super.stats)); | ||
} | ||
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static int | ||
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@@ -551,7 +580,8 @@ uct_dc_mlx5_iface_dci_put(uct_dc_mlx5_iface_t *iface, uint8_t dci_index) | |
ep = uct_dc_mlx5_ep_from_dci(iface, dci_index); | ||
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if (ucs_unlikely(ep == NULL)) { | ||
if (!uct_dc_mlx5_iface_dci_has_outstanding(iface, dci_index)) { | ||
if (!uct_dc_mlx5_iface_dci_has_outstanding(iface, dci_index) && | ||
!uct_dc_mlx5_is_hw_dci(iface, dci_index)) { | ||
uct_dc_mlx5_iface_dci_release(iface, dci_index); | ||
} | ||
return; | ||
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@@ -561,7 +591,7 @@ uct_dc_mlx5_iface_dci_put(uct_dc_mlx5_iface_t *iface, uint8_t dci_index) | |
ucs_assert(iface->tx.dci_pool[pool_index].stack_top > 0); | ||
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if (uct_dc_mlx5_iface_dci_has_outstanding(iface, dci_index)) { | ||
if (iface->tx.policy == UCT_DC_TX_POLICY_DCS_QUOTA) { | ||
if (uct_dc_mlx5_iface_is_dcs_quota_or_hybrid(iface)) { | ||
/* in tx_wait state: | ||
* - if there are no eps are waiting for dci allocation | ||
* ep goes back to normal state | ||
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@@ -609,6 +639,7 @@ uct_dc_mlx5_iface_dci_alloc(uct_dc_mlx5_iface_t *iface, uct_dc_mlx5_ep_t *ep) | |
"stack_top=%u, array_length(stack)=%u", pool->stack_top, | ||
ucs_array_length(&pool->stack)); | ||
ep->dci = ucs_array_elem(&pool->stack, pool->stack_top); | ||
ucs_assert(!uct_dc_mlx5_is_hw_dci(iface, ep->dci)); | ||
ucs_assert(uct_dc_mlx5_ep_from_dci(iface, ep->dci) == NULL); | ||
uct_dc_mlx5_iface_dci(iface, ep->dci)->ep = ep; | ||
pool->stack_top++; | ||
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@@ -637,7 +668,6 @@ uct_dc_mlx5_iface_dci_schedule_release(uct_dc_mlx5_iface_t *iface, uint8_t dci) | |
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iface->tx.dci_pool_release_bitmap |= UCS_BIT(pool_index); | ||
ucs_array_elem(&iface->tx.dci_pool[pool_index].stack, stack_top) = dci; | ||
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ucs_callbackq_add_oneshot(&worker->progress_q, iface, | ||
uct_dc_mlx5_ep_dci_release_progress, iface); | ||
} | ||
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@@ -651,7 +681,8 @@ uct_dc_mlx5_iface_dci_detach(uct_dc_mlx5_iface_t *iface, uct_dc_mlx5_ep_t *ep) | |
ucs_assert(dci_index != UCT_DC_MLX5_EP_NO_DCI); | ||
ucs_assert(iface->tx.dci_pool[uct_dc_mlx5_ep_pool_index(ep)].stack_top > 0); | ||
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if (uct_dc_mlx5_iface_dci_has_outstanding(iface, dci_index)) { | ||
if (uct_dc_mlx5_iface_dci_has_outstanding(iface, dci_index) || | ||
uct_dc_mlx5_is_hw_dci(iface, dci_index)) { | ||
return 0; | ||
} | ||
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@@ -666,6 +697,20 @@ uct_dc_mlx5_iface_dci_detach(uct_dc_mlx5_iface_t *iface, uct_dc_mlx5_ep_t *ep) | |
int uct_dc_mlx5_ep_is_connected(const uct_ep_h tl_ep, | ||
const uct_ep_is_connected_params_t *params); | ||
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static UCS_F_ALWAYS_INLINE ucs_status_t | ||
uct_dc_mlx5_set_ep_to_hw_dcs(uct_dc_mlx5_iface_t *iface, uct_dc_mlx5_ep_t *ep) | ||
{ | ||
if (!uct_dc_mlx5_iface_is_hybrid(iface) || | ||
!uct_dc_mlx5_iface_dci_has_tx_resources(iface, | ||
UCT_DC_MLX5_HW_DCI_INDEX)) { | ||
UCS_STATS_UPDATE_COUNTER(ep->super.stats, UCT_EP_STAT_NO_RES, 1); | ||
return UCS_ERR_NO_RESOURCE; | ||
} | ||
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ep->dci = UCT_DC_MLX5_HW_DCI_INDEX; | ||
return UCS_OK; | ||
} | ||
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static UCS_F_ALWAYS_INLINE ucs_status_t | ||
uct_dc_mlx5_iface_dci_get(uct_dc_mlx5_iface_t *iface, uct_dc_mlx5_ep_t *ep) | ||
{ | ||
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@@ -677,7 +722,8 @@ uct_dc_mlx5_iface_dci_get(uct_dc_mlx5_iface_t *iface, uct_dc_mlx5_ep_t *ep) | |
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ucs_assert(!iface->super.super.config.tx_moderation); | ||
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if (uct_dc_mlx5_iface_is_dci_shared(iface)) { | ||
if (uct_dc_mlx5_iface_is_dci_shared(iface) || | ||
uct_dc_mlx5_is_hw_dci(iface, ep->dci)) { | ||
Comment on lines
+725
to
+726
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. seems these two check are frequently used together. separate func is worth creating |
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/* Silence Coverity - in random policy the endpoint always has an | ||
* assigned DCI */ | ||
ucs_assert(ep->dci != UCT_DC_MLX5_EP_NO_DCI); | ||
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@@ -692,7 +738,7 @@ uct_dc_mlx5_iface_dci_get(uct_dc_mlx5_iface_t *iface, uct_dc_mlx5_ep_t *ep) | |
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if (ep->dci != UCT_DC_MLX5_EP_NO_DCI) { | ||
/* dci is already assigned - keep using it */ | ||
if ((iface->tx.policy == UCT_DC_TX_POLICY_DCS_QUOTA) && | ||
if (uct_dc_mlx5_iface_is_dcs_quota_or_hybrid(iface) && | ||
(ep->flags & UCT_DC_MLX5_EP_FLAG_TX_WAIT)) { | ||
goto out_no_res; | ||
} | ||
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@@ -703,10 +749,9 @@ uct_dc_mlx5_iface_dci_get(uct_dc_mlx5_iface_t *iface, uct_dc_mlx5_ep_t *ep) | |
txqp = &dci->txqp; | ||
available = uct_rc_txqp_available(txqp); | ||
waitq = uct_dc_mlx5_iface_dci_waitq(iface, pool_index); | ||
if ((iface->tx.policy == UCT_DC_TX_POLICY_DCS_QUOTA) && | ||
if (uct_dc_mlx5_iface_is_dcs_quota_or_hybrid(iface) && | ||
(available <= iface->tx.available_quota) && | ||
!ucs_arbiter_is_empty(waitq)) | ||
{ | ||
!ucs_arbiter_is_empty(waitq)) { | ||
ep->flags |= UCT_DC_MLX5_EP_FLAG_TX_WAIT; | ||
goto out_no_res; | ||
} | ||
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@@ -725,7 +770,9 @@ uct_dc_mlx5_iface_dci_get(uct_dc_mlx5_iface_t *iface, uct_dc_mlx5_ep_t *ep) | |
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uct_dc_mlx5_iface_dci_alloc(iface, ep); | ||
return UCS_OK; | ||
} | ||
} | ||
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return uct_dc_mlx5_set_ep_to_hw_dcs(iface, ep); | ||
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out_no_res: | ||
/* we will have to wait until someone releases dci */ | ||
|
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why just one channel and not
self->tx.num_dci_channels
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It doesn't matter as this dci is only created to query
bb_max
and then destroyed (lines 913-914)There was a problem hiding this comment.
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ic, probably need to change the name of this func, as it is quite confusing currently