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UCT/IB/MLX5/DC: introducing dcs_hybrid policy #10138

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UCT/IB/MLX5/DC: introducing dcs_hybrid policy #10138

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65046c8
UCT/IB/MLX5/DC: introducing dcs_hybrid policy
roiedanino Sep 5, 2024
e2510f5
UCT/IB/MLX5/DC: reduced branches in fast path
roiedanino Sep 10, 2024
9bace1e
UCT/IB/MLX5/DC: tiny - clang-format (space)
roiedanino Sep 10, 2024
1796b18
UCT/IB/MLX5/DC: use iface attribute to avoid extra branches
roiedanino Sep 19, 2024
8aa351f
Merge branch 'master' into hw-dcs-2
roiedanino Sep 19, 2024
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27 changes: 17 additions & 10 deletions src/uct/ib/mlx5/dc/dc_mlx5.c
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Original file line number Diff line number Diff line change
Expand Up @@ -29,11 +29,12 @@


const char *uct_dc_tx_policy_names[] = {
[UCT_DC_TX_POLICY_DCS] = "dcs",
[UCT_DC_TX_POLICY_DCS_QUOTA] = "dcs_quota",
[UCT_DC_TX_POLICY_RAND] = "rand",
[UCT_DC_TX_POLICY_HW_DCS] = "hw_dcs",
[UCT_DC_TX_POLICY_LAST] = NULL
[UCT_DC_TX_POLICY_DCS] = "dcs",
[UCT_DC_TX_POLICY_DCS_QUOTA] = "dcs_quota",
[UCT_DC_TX_POLICY_DCS_HYBRID] = "dcs_hybrid",
[UCT_DC_TX_POLICY_RAND] = "rand",
[UCT_DC_TX_POLICY_HW_DCS] = "hw_dcs",
[UCT_DC_TX_POLICY_LAST] = NULL
};

static const char *uct_dct_affinity_policy_names[] = {
Expand Down Expand Up @@ -366,7 +367,8 @@ static void uct_ib_mlx5dv_dci_qp_init_attr(uct_ib_qp_init_attr_t *qp_attr,
}

ucs_status_t uct_dc_mlx5_iface_create_dci(uct_dc_mlx5_iface_t *iface,
uint8_t dci_index, int connect)
uint8_t dci_index, int connect,
uint8_t num_dci_channels)
{
uct_ib_iface_t *ib_iface = &iface->super.super.super;
uct_ib_mlx5_qp_attr_t attr = {};
Expand All @@ -391,7 +393,7 @@ ucs_status_t uct_dc_mlx5_iface_create_dci(uct_dc_mlx5_iface_t *iface,
UCT_DC_MLX5_IFACE_FLAG_DCI_FULL_HANDSHAKE;
attr.rdma_wr_disabled = (iface->flags & UCT_DC_MLX5_IFACE_FLAG_DISABLE_PUT) &&
(md->flags & UCT_IB_MLX5_MD_FLAG_NO_RDMA_WR_OPTIMIZED);
attr.log_num_dci_stream_channels = ucs_ilog2(iface->tx.num_dci_channels);
attr.log_num_dci_stream_channels = ucs_ilog2(num_dci_channels);
status = uct_ib_mlx5_devx_create_qp(ib_iface,
&iface->super.cq[UCT_IB_DIR_TX],
&iface->super.cq[UCT_IB_DIR_RX],
Expand Down Expand Up @@ -901,7 +903,7 @@ uct_dc_mlx5_iface_dcis_create(uct_dc_mlx5_iface_t *iface,

ucs_array_length(&iface->tx.dcis) = 0;

status = uct_dc_mlx5_iface_create_dci(iface, 0, 0);
status = uct_dc_mlx5_iface_create_dci(iface, 0, 0, 1);
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why just one channel and not self->tx.num_dci_channels?

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It doesn't matter as this dci is only created to query bb_max and then destroyed (lines 913-914)

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ic, probably need to change the name of this func, as it is quite confusing currently

if (status != UCS_OK) {
return status;
}
Expand Down Expand Up @@ -1355,7 +1357,8 @@ static void uct_dc_mlx5_dci_handle_failure(uct_dc_mlx5_iface_t *iface,
uct_dc_mlx5_ep_t *ep;
ucs_log_level_t level;

if (uct_dc_mlx5_iface_is_dci_shared(iface)) {
if (uct_dc_mlx5_iface_is_dci_shared(iface) ||
uct_dc_mlx5_is_hw_dci(iface, dci_index)) {
ep = NULL;
level = UCS_LOG_LEVEL_FATAL; /* error handling is not supported with rand dci */
} else {
Expand Down Expand Up @@ -1593,6 +1596,9 @@ static UCS_CLASS_INIT_FUNC(uct_dc_mlx5_iface_t, uct_md_h tl_md, uct_worker_h wor
self->tx.dcis_initial_capacity =
ucs_min(config->dcis_initial_capacity,
self->tx.ndci * UCT_DC_MLX5_IFACE_MAX_DCI_POOLS);
self->tx.hybrid_hw_dci = uct_dc_mlx5_iface_is_hybrid(self) ?
UCT_DC_MLX5_HW_DCI_INDEX :
-1;

init_attr.qp_type = UCT_IB_QPT_DCI;
init_attr.flags = UCT_IB_TX_OPS_PER_PATH;
Expand Down Expand Up @@ -1663,7 +1669,8 @@ static UCS_CLASS_INIT_FUNC(uct_dc_mlx5_iface_t, uct_md_h tl_md, uct_worker_h wor
return UCS_ERR_INVALID_PARAM;
}

if (uct_dc_mlx5_iface_is_hw_dcs(self)) {
if (uct_dc_mlx5_iface_is_hw_dcs(self) ||
uct_dc_mlx5_iface_is_hybrid(self)) {
/* Calculate num_dci_channels: select minimum from requested by runtime
* and supported by HCA, must be power of two */
num_dci_channels = ucs_roundup_pow2(config->num_dci_channels);
Expand Down
7 changes: 6 additions & 1 deletion src/uct/ib/mlx5/dc/dc_mlx5.h
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Original file line number Diff line number Diff line change
Expand Up @@ -147,6 +147,7 @@ typedef enum {
/* Policies with dedicated DCI per active connection */
UCT_DC_TX_POLICY_DCS,
UCT_DC_TX_POLICY_DCS_QUOTA,
UCT_DC_TX_POLICY_DCS_HYBRID,
/* Policies with shared DCI */
UCT_DC_TX_POLICY_SHARED_FIRST,
UCT_DC_TX_POLICY_RAND = UCT_DC_TX_POLICY_SHARED_FIRST,
Expand Down Expand Up @@ -333,6 +334,9 @@ struct uct_dc_mlx5_iface {
uint8_t num_dci_channels;

uint16_t dcis_initial_capacity;

/* used in hybrid dcs policy otherwise -1 */
int8_t hybrid_hw_dci;
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} tx;

struct {
Expand Down Expand Up @@ -392,7 +396,8 @@ void uct_dc_mlx5_iface_set_ep_failed(uct_dc_mlx5_iface_t *iface,
void uct_dc_mlx5_iface_reset_dci(uct_dc_mlx5_iface_t *iface, uint8_t dci_index);

ucs_status_t uct_dc_mlx5_iface_create_dci(uct_dc_mlx5_iface_t *iface,
uint8_t dci_index, int connect);
uint8_t dci_index, int connect,
uint8_t num_dci_channels);

ucs_status_t uct_dc_mlx5_iface_resize_and_fill_dcis(uct_dc_mlx5_iface_t *iface,
uint16_t size);
Expand Down
9 changes: 5 additions & 4 deletions src/uct/ib/mlx5/dc/dc_mlx5_ep.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1283,7 +1283,8 @@ UCS_CLASS_CLEANUP_FUNC(uct_dc_mlx5_ep_t)
uct_dc_mlx5_ep_fc_cleanup(self);

if ((self->dci == UCT_DC_MLX5_EP_NO_DCI) ||
uct_dc_mlx5_iface_is_dci_shared(iface)) {
uct_dc_mlx5_iface_is_dci_shared(iface) ||
uct_dc_mlx5_is_hw_dci(iface, self->dci)) {
return;
}

Expand Down Expand Up @@ -1394,12 +1395,12 @@ uct_dc_mlx5_iface_dci_do_pending_wait(ucs_arbiter_t *arbiter,
ep, iface, ep->dci,
uct_dc_mlx5_iface_dci(iface, ep->dci)->pool_index);

if (!uct_dc_mlx5_iface_dci_can_alloc_or_create(iface, pool_index)) {
if (uct_dc_mlx5_iface_dci_can_alloc_or_create(iface, pool_index)) {
uct_dc_mlx5_iface_dci_alloc(iface, ep);
} else if (uct_dc_mlx5_set_ep_to_hw_dcs(iface, ep) != UCS_OK) {
return UCS_ARBITER_CB_RESULT_STOP;
}

uct_dc_mlx5_iface_dci_alloc(iface, ep);

ucs_assert_always(ep->dci != UCT_DC_MLX5_EP_NO_DCI);
uct_dc_mlx5_iface_dci_sched_tx(iface, ep);
return UCS_ARBITER_CB_RESULT_DESCHED_GROUP;
Expand Down
91 changes: 69 additions & 22 deletions src/uct/ib/mlx5/dc/dc_mlx5_ep.h
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Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,8 @@

#include "dc_mlx5.h"

#define UCT_DC_MLX5_EP_NO_DCI ((uint8_t)-1)
#define UCT_DC_MLX5_EP_NO_DCI ((uint8_t)-1)
#define UCT_DC_MLX5_HW_DCI_INDEX 0


#define UCT_DC_MLX5_TXQP_DECL(_txqp, _txwq) \
Expand Down Expand Up @@ -266,6 +267,19 @@ uct_dc_mlx5_iface_is_dci_shared(const uct_dc_mlx5_iface_t *iface)
return iface->tx.policy >= UCT_DC_TX_POLICY_SHARED_FIRST;
}

static UCS_F_ALWAYS_INLINE int
uct_dc_mlx5_iface_is_dcs_quota_or_hybrid(const uct_dc_mlx5_iface_t *iface)
{
return UCS_BIT(iface->tx.policy) & (UCS_BIT(UCT_DC_TX_POLICY_DCS_QUOTA) |
UCS_BIT(UCT_DC_TX_POLICY_DCS_HYBRID));
}

static UCS_F_ALWAYS_INLINE int
uct_dc_mlx5_iface_is_hybrid(const uct_dc_mlx5_iface_t *iface)
{
return iface->tx.policy == UCT_DC_TX_POLICY_DCS_HYBRID;
}
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static UCS_F_ALWAYS_INLINE ucs_arbiter_group_t*
uct_dc_mlx5_ep_rand_arb_group(uct_dc_mlx5_iface_t *iface, uct_dc_mlx5_ep_t *ep)
{
Expand Down Expand Up @@ -315,18 +329,30 @@ uct_dc_mlx5_init_dci_config(uct_dc_mlx5_dci_config_t *dci_config,
dci_config->max_rd_atomic = max_rd_atomic;
}

static UCS_F_ALWAYS_INLINE int
uct_dc_mlx5_is_hw_dci(const uct_dc_mlx5_iface_t *iface, uint8_t dci)
{
return dci == iface->tx.hybrid_hw_dci;
}

ucs_status_t static UCS_F_ALWAYS_INLINE
uct_dc_mlx5_dci_pool_init_dci(uct_dc_mlx5_iface_t *iface, uint8_t pool_index,
uint8_t dci_index)
{
uct_dc_mlx5_dci_pool_t *pool = &iface->tx.dci_pool[pool_index];
uct_dc_dci_t *dci = uct_dc_mlx5_iface_dci(iface, dci_index);
uint8_t num_channels = 1;
ucs_status_t status;

ucs_assertv(ucs_array_length(&pool->stack) < iface->tx.ndci,
"stack length exceeded ndci");

status = uct_dc_mlx5_iface_create_dci(iface, dci_index, 1);
if (uct_dc_mlx5_iface_is_hw_dcs(iface) ||
uct_dc_mlx5_is_hw_dci(iface, dci_index)) {
num_channels = iface->tx.num_dci_channels;
}

status = uct_dc_mlx5_iface_create_dci(iface, dci_index, 1, num_channels);
if (status != UCS_OK) {
ucs_error("iface %p: failed to create dci %u at pool %u", iface,
dci_index, pool_index);
Expand All @@ -342,11 +368,19 @@ uct_dc_mlx5_dci_pool_init_dci(uct_dc_mlx5_iface_t *iface, uint8_t pool_index,
static UCS_F_ALWAYS_INLINE ucs_status_t
uct_dc_mlx5_ep_basic_init(uct_dc_mlx5_iface_t *iface, uct_dc_mlx5_ep_t *ep)
{
uct_dc_dci_t *dci;
size_t dcis_array_size;
uct_dc_dci_t *dci;

ucs_arbiter_group_init(&ep->arb_group);

if ((uct_dc_mlx5_iface_is_hw_dcs(iface) ||
uct_dc_mlx5_iface_is_hybrid(iface)) &&
ucs_array_is_empty(&iface->tx.dcis)) {
uct_dc_mlx5_iface_resize_and_fill_dcis(iface, 1);
uct_dc_mlx5_dci_pool_init_dci(iface, uct_dc_mlx5_ep_pool_index(ep),
UCT_DC_MLX5_HW_DCI_INDEX);
}

if (uct_dc_mlx5_iface_is_dci_rand(iface)) {
/* coverity[dont_call] */
ep->dci = rand_r(&iface->tx.rand_seed) % iface->tx.ndci;
Expand All @@ -360,22 +394,17 @@ uct_dc_mlx5_ep_basic_init(uct_dc_mlx5_iface_t *iface, uct_dc_mlx5_ep_t *ep)
ep->dci);
}
} else if (uct_dc_mlx5_iface_is_hw_dcs(iface)) {
ucs_assertv(iface->tx.ndci == 1, "ndci=%u", iface->tx.ndci);
if (ucs_array_is_empty(&iface->tx.dcis)) {
uct_dc_mlx5_iface_resize_and_fill_dcis(iface, 1);
uct_dc_mlx5_dci_pool_init_dci(iface, uct_dc_mlx5_ep_pool_index(ep),
0);
}
ep->dci = 0;
ep->dci = UCT_DC_MLX5_HW_DCI_INDEX;
dci = uct_dc_mlx5_iface_dci(iface, ep->dci);
ep->dci_channel_index = dci->next_channel_index++;
} else {
/* Hybrid or software dcs */
ep->dci = UCT_DC_MLX5_EP_NO_DCI;
ep->dci_channel_index = 0;
}

return uct_rc_fc_init(&ep->fc, &iface->super.super
UCS_STATS_ARG(ep->super.stats));
return uct_rc_fc_init(&ep->fc,
&iface->super.super UCS_STATS_ARG(ep->super.stats));
}

static int
Expand Down Expand Up @@ -551,7 +580,8 @@ uct_dc_mlx5_iface_dci_put(uct_dc_mlx5_iface_t *iface, uint8_t dci_index)
ep = uct_dc_mlx5_ep_from_dci(iface, dci_index);

if (ucs_unlikely(ep == NULL)) {
if (!uct_dc_mlx5_iface_dci_has_outstanding(iface, dci_index)) {
if (!uct_dc_mlx5_iface_dci_has_outstanding(iface, dci_index) &&
!uct_dc_mlx5_is_hw_dci(iface, dci_index)) {
uct_dc_mlx5_iface_dci_release(iface, dci_index);
}
return;
Expand All @@ -561,7 +591,7 @@ uct_dc_mlx5_iface_dci_put(uct_dc_mlx5_iface_t *iface, uint8_t dci_index)
ucs_assert(iface->tx.dci_pool[pool_index].stack_top > 0);

if (uct_dc_mlx5_iface_dci_has_outstanding(iface, dci_index)) {
if (iface->tx.policy == UCT_DC_TX_POLICY_DCS_QUOTA) {
if (uct_dc_mlx5_iface_is_dcs_quota_or_hybrid(iface)) {
/* in tx_wait state:
* - if there are no eps are waiting for dci allocation
* ep goes back to normal state
Expand Down Expand Up @@ -609,6 +639,7 @@ uct_dc_mlx5_iface_dci_alloc(uct_dc_mlx5_iface_t *iface, uct_dc_mlx5_ep_t *ep)
"stack_top=%u, array_length(stack)=%u", pool->stack_top,
ucs_array_length(&pool->stack));
ep->dci = ucs_array_elem(&pool->stack, pool->stack_top);
ucs_assert(!uct_dc_mlx5_is_hw_dci(iface, ep->dci));
ucs_assert(uct_dc_mlx5_ep_from_dci(iface, ep->dci) == NULL);
uct_dc_mlx5_iface_dci(iface, ep->dci)->ep = ep;
pool->stack_top++;
Expand Down Expand Up @@ -637,7 +668,6 @@ uct_dc_mlx5_iface_dci_schedule_release(uct_dc_mlx5_iface_t *iface, uint8_t dci)

iface->tx.dci_pool_release_bitmap |= UCS_BIT(pool_index);
ucs_array_elem(&iface->tx.dci_pool[pool_index].stack, stack_top) = dci;

ucs_callbackq_add_oneshot(&worker->progress_q, iface,
uct_dc_mlx5_ep_dci_release_progress, iface);
}
Expand All @@ -651,7 +681,8 @@ uct_dc_mlx5_iface_dci_detach(uct_dc_mlx5_iface_t *iface, uct_dc_mlx5_ep_t *ep)
ucs_assert(dci_index != UCT_DC_MLX5_EP_NO_DCI);
ucs_assert(iface->tx.dci_pool[uct_dc_mlx5_ep_pool_index(ep)].stack_top > 0);

if (uct_dc_mlx5_iface_dci_has_outstanding(iface, dci_index)) {
if (uct_dc_mlx5_iface_dci_has_outstanding(iface, dci_index) ||
uct_dc_mlx5_is_hw_dci(iface, dci_index)) {
return 0;
}

Expand All @@ -666,6 +697,20 @@ uct_dc_mlx5_iface_dci_detach(uct_dc_mlx5_iface_t *iface, uct_dc_mlx5_ep_t *ep)
int uct_dc_mlx5_ep_is_connected(const uct_ep_h tl_ep,
const uct_ep_is_connected_params_t *params);

static UCS_F_ALWAYS_INLINE ucs_status_t
uct_dc_mlx5_set_ep_to_hw_dcs(uct_dc_mlx5_iface_t *iface, uct_dc_mlx5_ep_t *ep)
{
if (!uct_dc_mlx5_iface_is_hybrid(iface) ||
!uct_dc_mlx5_iface_dci_has_tx_resources(iface,
UCT_DC_MLX5_HW_DCI_INDEX)) {
UCS_STATS_UPDATE_COUNTER(ep->super.stats, UCT_EP_STAT_NO_RES, 1);
return UCS_ERR_NO_RESOURCE;
}

ep->dci = UCT_DC_MLX5_HW_DCI_INDEX;
return UCS_OK;
}

static UCS_F_ALWAYS_INLINE ucs_status_t
uct_dc_mlx5_iface_dci_get(uct_dc_mlx5_iface_t *iface, uct_dc_mlx5_ep_t *ep)
{
Expand All @@ -677,7 +722,8 @@ uct_dc_mlx5_iface_dci_get(uct_dc_mlx5_iface_t *iface, uct_dc_mlx5_ep_t *ep)

ucs_assert(!iface->super.super.config.tx_moderation);

if (uct_dc_mlx5_iface_is_dci_shared(iface)) {
if (uct_dc_mlx5_iface_is_dci_shared(iface) ||
uct_dc_mlx5_is_hw_dci(iface, ep->dci)) {
Comment on lines +725 to +726
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seems these two check are frequently used together. separate func is worth creating

/* Silence Coverity - in random policy the endpoint always has an
* assigned DCI */
ucs_assert(ep->dci != UCT_DC_MLX5_EP_NO_DCI);
Expand All @@ -692,7 +738,7 @@ uct_dc_mlx5_iface_dci_get(uct_dc_mlx5_iface_t *iface, uct_dc_mlx5_ep_t *ep)

if (ep->dci != UCT_DC_MLX5_EP_NO_DCI) {
/* dci is already assigned - keep using it */
if ((iface->tx.policy == UCT_DC_TX_POLICY_DCS_QUOTA) &&
if (uct_dc_mlx5_iface_is_dcs_quota_or_hybrid(iface) &&
(ep->flags & UCT_DC_MLX5_EP_FLAG_TX_WAIT)) {
goto out_no_res;
}
Expand All @@ -703,10 +749,9 @@ uct_dc_mlx5_iface_dci_get(uct_dc_mlx5_iface_t *iface, uct_dc_mlx5_ep_t *ep)
txqp = &dci->txqp;
available = uct_rc_txqp_available(txqp);
waitq = uct_dc_mlx5_iface_dci_waitq(iface, pool_index);
if ((iface->tx.policy == UCT_DC_TX_POLICY_DCS_QUOTA) &&
if (uct_dc_mlx5_iface_is_dcs_quota_or_hybrid(iface) &&
(available <= iface->tx.available_quota) &&
!ucs_arbiter_is_empty(waitq))
{
!ucs_arbiter_is_empty(waitq)) {
ep->flags |= UCT_DC_MLX5_EP_FLAG_TX_WAIT;
goto out_no_res;
}
Expand All @@ -725,7 +770,9 @@ uct_dc_mlx5_iface_dci_get(uct_dc_mlx5_iface_t *iface, uct_dc_mlx5_ep_t *ep)

uct_dc_mlx5_iface_dci_alloc(iface, ep);
return UCS_OK;
}
}

return uct_dc_mlx5_set_ep_to_hw_dcs(iface, ep);

out_no_res:
/* we will have to wait until someone releases dci */
Expand Down
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