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John Bieling edited this page Mar 15, 2016 · 32 revisions

The jTDC is an FPGA based high resolution TDC implemented on Xilinx Spartan 6 and compatible FPGAs. It is used at the BGO-OD experiment located at the ELSA facility in Bonn/Germany. The first prototype was developed on a Xilinx Virtex 5 FPGA for the COMPASS experiment located at CERN.

As a proof of concept, this repository not only contains the sources for the core modules of the jTDC, but also two complete example implementations for the VFB6 FPGA board manufactured by ELB. I will include any other working implementation for other FPGA boards, if provided.

Overview example implementations for the VFB6 board

The VFB6 board has the following I/O:

  • 3 mezzanine input/output card connectors (A, B and C)
  • 4 NIM connectors, each configurable as input or output

The first example implementation (a.k.a. LVDS version) is designed for using LVDS INPUT cards (32 LVDS inputs per mezzanine, thus 96 channel in total), the second implementation (a.k.a. DISC version) is designed for the DISCRIMINATOR INPUT cards (16 analog inputs per mezzanine, thus 48 channels in total). The discriminators operate independent from the FPGA, it only receives the discriminated time-over-treshold (ToT) signal. The DISC version is recording both edges of the discriminated signal, to be able to extract the ToT information from the data.

Besides the 96 LVDS / 48 analog input channels, two of the NIM inputs are recorded by the TDC, one of them can be used as trigger input.

General features of the jTDC

  • Up to 100 TDC channels per board with 40ps average bin size (30ps RMS **).
  • All inputs can be inverted.
  • Scalers (32bit @200MHz) for every input channel, which can also operate in duty cycle mode.
  • Scalers support a lifetime-count-mode, if DAQ provides a busy signal
  • Maximum input rate without missing hits: 200MHz ** (valid for all inputs at the same time).
  • Minimum length of input signals: 3ns **
  • Double pulse resolution: 5ns **
  • Max hits per event stored in DATA-FIFO: 15.360, limiting the trigger window to 775ns at full rate on all channels (at lower rate limited by BRAM size to 1250ns).
  • Readout during lifetime.
  • 2 Trigger outputs available (logical OR of all input signals or subsets)

** These features are limited by the hardware (Xilinx Spartan 6 / VFB6) and cannot be easily improved. All other limits are limits by choice (only 17% of RAM resources used, so plenty of space for more channels/larger FIFOs).

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