3 Example Implementations

All example implementations can be configured, monitored and read-out by jDaqLite.

At current, there are only two example implementations which are designed for the VFB6 FPGA board (↗) manufactured by ELB (↗) with two different input card configurations. I will include any other working implementation for other FPGA boards, if provided.

The VFB6 board has the following I/O:

• 3 mezzanine input/output card connectors
• 4 NIM connectors, each configurable as input or output

The first VFB6 implementation (a.k.a. VFB6-LVDS Version) is designed for the LVDS INPUT cards (32 LVDS inputs per mezzanine, thus 96 channel in total), the second VFB6 implementation (a.k.a. VFB6-DISC Version) is designed for the DISCRIMINATOR INPUT cards (16 analog inputs per mezzanine, thus 48 channels in total). The discriminators operate independent from the FPGA, it only receives the discriminated time-over-treshold (ToT) signal. The DISC version is recording both edges of the discriminated signal, to be able to extract the ToT information from the data.

Besides the 96 LVDS / 48 analog input channels, two of the NIM inputs are recorded by the TDC, one of them can be used as trigger input.