-
Notifications
You must be signed in to change notification settings - Fork 26
3.2 VFB6 DISC
This example implementation of the jTDC is designed for the VFB6 board from ELB using 3 DISCRIMINATER mezzanine cards. It's inputs and outputs are mapped as follows:
- MEZA: analog input channel 01-16
- MEZB: analog input channel 17-32
- MEZC: analog input channel 33-48
- NIM[0]: Channel 0 input (trigger and busy) input (frontpanel, left NIM socket)
- NIM[1]: Trigger A output (frontpanel, right NIM socket)
- NIM[2]: Channel 49 input (backpanel, left NIM socket)
- NIM[3]: Trigger B output (backpanel, right NIM socket)
The FPGA only sees the discriminated time-over-threshold signals and samples BOTH edges. The trailing edges of input channels 01-48 are stored as tdc channels 51-98.
All registers are 32bit registers and you must read/write all 32bits, even if you want to change/set/get only a specific bit. Some registers are so called toggle registers, they toggle back to 0x00000000 after one clock cycle and are used to trigger events (for example resets). The read value from such a toggle register has mostly a completely different source (for example status information) and has nothing to do with the toggle state of the register.
| address |
16bit bitmask to enable/disable channels (highest 16bit of 32bit registers are not used) |
| 0xbase2000 | DISC input channels 16 - 01 |
| 0xbase2004 | DISC input channels 32 - 17 |
| 0xbase2008 | DISC input channels 48 - 33 |
This is a configuration register, you can readback the current values at any given time.
| bits | config value |
| 4-0 | Set GeoID of the module. This ID is written into the header data of each event. |
| 5 | Set to 1 to enable dutycycle count mode (check input state each clk cycle and count if state is high) |
| 6 | Set to 1 to invert all inputs |
| 7 | Set to 1 to use DISC_A_IN[0] instead of NIM[0] as trigger input |
| 15-8 | Set maximum trigger window size to (N*5)ns (max 1250ns) |
This is a configuration register, you can readback the current values at any given time.
| bits | config value |
| 8-0 | busyshift** (0-2500ns in steps of 5ns) |
| 9 | enable lifetime gate for counters (stop counting on busy)** |
| 15-11 | busyextend (0-155ns in steps of 5ns, must not be larger than length of busy)** |
| 19-16 | high time (length) setting for trigger output: (5*N + 10)ns |
| 23-20 | dead time setting for trigger output: (5*N + 10)ns |
| 26-24 | 3bit mask for trigger output NIM[1] to select OR of DISC_C, DISC_B and/or DISC_A (0x7 will put the logical OR of all DISC inputs on NIM[1], 0x2 just those of DISC_B) |
| 29-27 | 3bit mask for trigger output NIM[3] to select OR of DISC_C, DISC_B and/or DISC_A (0x7 will put the logical OR of all DISC inputs on NIM[3], 0x2 just those of DISC_B) |
| 30 | disable external latch (scalers will not be latched by the trigger input) |
This is a configuration register, you can readback the current values at any given time.
** The trigger-input is used twofold: Its leading edge is used as trigger and its length is used as DAQ deadtime/busy indicator. If the DAQ keeps the trigger signal active until it has finished processing it (read-out of all TDCs), the jTDC can use that information as a life-time-gate for its input scalers. To cope with extra delay due to cables and other elements, the busy signal can be shifted and extended.
| bit | toggle actions |
| 0 | TDC reset |
| 1 | counter reset |
| 2 | counter latch |
| 3 | output reset (must be called after changing the high- or dead time settings, and after initial fw load) |
This is a toggle register, the readback value of this register contains the following information:
| bit | value |
| 7-0 | firmware version |
| 15-8 | module id |
| 23-16 | number of encoded bits per channel |
| 31-24 | number of tdc channels |
CAUTION! The scalers cannot be addressed directly! First read the clock counter and then read register 0xbase4000 98 times to get the 98 scaler values. For convenience, the addressbus is masked for register 0xbase4000, so one could also consecutively read address 0xbase4000 to 0xbase409B.
| address | value in read-only register |
| 0xbase0044 | clock counter (a read request sets the current read-out scaler to channel 0) |
| 0xbase4000 | scaler value of the current read-out scaler (auto incrementation of the current read-out scaler) |
The following settings are written into registers of DAQs on the discriminator input card to set different voltages. For the threshold, an analog comparator is used to detect when the input signal is above threshold, thus discriminating the analog input signals. The hysterese setting is added to the threshold for the start-of-signal-detection and subtracted from the threshold for the end-of-signal-detection.
Furthermore, the DAQs can be fine-tuned by additional offset settings. For more information please contact ELB.
The index in the following table is used as follows: 0=all ch, 1-16=ch, 17=offset daq 1a, 18=offset daq 1b, 19=offset daq 2a, 20=offset daq 2b.
| address | pattern of dataword to set |
| 0xbaseA004 | write any value in this reg to initialize MEZA |
| 0xbaseA044 | write any value in this reg to initialize MEZB |
| 0xbaseA084 | write any value in this reg to initialize MEZC |
| 0xbaseA010 | set thresholds for index of MEZA via {5bit index,16bit value} |
| 0xbaseA050 | set thresholds for index of MEZB via {5bit index,16bit value} |
| 0xbaseA090 | set thresholds for index of MEZC via {5bit index,16bit value} |
| 0xbaseA020 | set hysterese for index of MEZA via {5bit index,16bit value} |
| 0xbaseA060 | set hysterese for index of MEZB via {5bit index,16bit value} |
| 0xbaseA0A0 | set hysterese for index of MEZC via {5bit index,16bit value} |
The discriminator input card also contains an ADC, which can be used to readback the actual voltages of the current thresholds, hystereses and others.
| address | analog readback value (one or two 16'bit words) |
| 0xbaseA100 + 4*i | {HYSTERESE & THRESHOLD} of channel i |
| 0xbaseA200 | {DAC1_OFFSETA & DAC1_OFFSETB} of MEZA |
| 0xbaseA204 | {DAC2_OFFSETA & DAC2_OFFSETB} of MEZA |
| 0xbaseA208 | {DAC1_REFA & DAC1_REFB} of MEZA |
| 0xbaseA20C | {DAC2_REFA & DAC2_REFB} of MEZA |
| 0xbaseA210 | {DAC_GND} of MEZA |
| 0xbaseA240 | {DAC1_OFFSETA & DAC1_OFFSETB} of MEZB |
| 0xbaseA244 | {DAC2_OFFSETA & DAC2_OFFSETB} of MEZB |
| 0xbaseA248 | {DAC1_REFA & DAC1_REFB} of MEZB |
| 0xbaseA24C | {DAC2_REFA & DAC2_REFB} of MEZB |
| 0xbaseA250 | {DAC_GND} of MEZB |
| 0xbaseA280 | {DAC1_OFFSETA & DAC1_OFFSETB} of MEZC |
| 0xbaseA284 | {DAC2_OFFSETA & DAC2_OFFSETB} of MEZC |
| 0xbaseA288 | {DAC1_REFA & DAC1_REFB} of MEZC |
| 0xbaseA28C | {DAC2_REFA & DAC2_REFB} of MEZC |
| 0xbaseA290 | {DAC_GND} of MEZC |