Pdlloyd add verilog syntax

[pdlloyd]

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Description

This pull request adds syntax highlighting support for SystemVerilog and Verilog. It adds https://github.com/TheClams/SystemVerilog as a submodule. Credit goes to the maintainers of this repository for the syntax files.

I saw here that additional syntaxes will be postponed for a while, and so I will add this syntax manually to my projects until then.

[Keats]

Thanks for the PR. I'm putting any changes to the syntax highlighting on hold though until #1787 has seen some progress to know whether it's viable