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Regarding logic analyzer input/output directionality in firmware and SoC

Status: Open.

#113 In efabless/caravel_board;

· jainsoumil2 opened on Mar 5, 2025

GFMPW-1 read compare FAILED

Status: Open.

#111 In efabless/caravel_board;

· gonsolo opened on Sep 9, 2024

Setting register value

Status: Open.

#109 In efabless/caravel_board;

· Rimal12345 opened on Jul 9, 2024

Caravel Rev 5B eval board: J6 (oscillator enable) & J2 (UART EN) label incorrect, misleading

Status: Open.

#108 In efabless/caravel_board;

· algofoogle opened on Jun 24, 2024

miniterm.py file for serial communication demo appears to be missing in the chipignite directory

Status: Open.

#107 In efabless/caravel_board;

· JamesTimothyMeech opened on Jun 21, 2024

Mismatch of GPIO mapping in defs.h and documentation

Status: Open.

#105 In efabless/caravel_board;

· IAmMarcelJung opened on Mar 19, 2024

add pdf schematic of the dev board

Status: Open.

#104 In efabless/caravel_board;

· mattvenn opened on Feb 23, 2024

Add libgcc to firmware examples Makefiles?

Status: Open.

#101 In efabless/caravel_board;

· mbalestrini opened on Feb 7, 2024

windows FTDI issues

Status: Open.

#95 In efabless/caravel_board;

· mattvenn opened on Jan 12, 2024

Mention J2 use for serial communication through USB on chipignite Readme

Status: Open.

#94 In efabless/caravel_board;

· mbalestrini opened on Jan 2, 2024

Recent versions of RISC-V gcc require "zicsr" in the compile line.

bugSomething isn't workingSomething isn't working

Status: Open.

#87 In efabless/caravel_board;

· RTimothyEdwards opened on Jul 21, 2023

dev-v5-M.2 component part numbers

Status: Open.

#77 In efabless/caravel_board;

· CarlFK opened on May 1, 2023