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Fix struct literal on pattern assignment (verilator#5552) (verilator#…
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#!/usr/bin/env python3 | ||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition | ||
# | ||
# Copyright 2024 by Wilson Snyder. This program is free software; you | ||
# can redistribute it and/or modify it under the terms of either the GNU | ||
# Lesser General Public License Version 3 or the Perl Artistic License | ||
# Version 2.0. | ||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 | ||
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import vltest_bootstrap | ||
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test.scenarios('simulator') | ||
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test.compile(verilator_flags2=["--debug"]) | ||
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test.execute() | ||
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test.passes() |
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// DESCRIPTION: Verilator: Demonstrate struct literal param assignment problem | ||
// | ||
// This file ONLY is placed into the Public Domain, for any use, | ||
// without warranty, 2024 by Wilson Snyder. | ||
// SPDX-License-Identifier: CC0-1.0 | ||
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package Some_pkg; | ||
typedef struct packed { | ||
int foo; | ||
} some_struct_t; | ||
endpackage | ||
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module sub #( | ||
parameter Some_pkg::some_struct_t the_some_struct | ||
) (); | ||
endmodule | ||
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module t (/*AUTOARG*/ | ||
// Inputs | ||
clk | ||
); | ||
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input clk; | ||
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// finish report | ||
always @ (posedge clk) begin | ||
$write("*-* All Finished *-*\n"); | ||
$finish; | ||
end | ||
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sub #( | ||
.the_some_struct( | ||
Some_pkg::some_struct_t'{ | ||
foo: 1 | ||
})) | ||
the_sub (); | ||
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endmodule |