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Fix struct literal on pattern assignment (verilator#5552) (verilator#…
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toddstrader authored Oct 24, 2024
1 parent fd2917c commit 83081aa
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Showing 3 changed files with 57 additions and 1 deletion.
2 changes: 1 addition & 1 deletion src/V3Width.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -5544,7 +5544,7 @@ class WidthVisitor final : public VNVisitor {
userIterate(modVarp->childDTypep(),
WidthVP{SELF, BOTH}.p()); // May relink pointed to node
AstNodeDType* const setDtp = modVarp->childDTypep()->cloneTree(false);
patternp->childDTypep(setDtp);
if (!patternp->childDTypep()) patternp->childDTypep(setDtp);
userIterateChildren(nodep, WidthVP{setDtp, BOTH}.p());
didWidth = true;
}
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18 changes: 18 additions & 0 deletions test_regress/t/t_struct_literal_param.py
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@@ -0,0 +1,18 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

import vltest_bootstrap

test.scenarios('simulator')

test.compile(verilator_flags2=["--debug"])

test.execute()

test.passes()
38 changes: 38 additions & 0 deletions test_regress/t/t_struct_literal_param.v
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@@ -0,0 +1,38 @@
// DESCRIPTION: Verilator: Demonstrate struct literal param assignment problem
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2024 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0

package Some_pkg;
typedef struct packed {
int foo;
} some_struct_t;
endpackage

module sub #(
parameter Some_pkg::some_struct_t the_some_struct
) ();
endmodule

module t (/*AUTOARG*/
// Inputs
clk
);

input clk;

// finish report
always @ (posedge clk) begin
$write("*-* All Finished *-*\n");
$finish;
end

sub #(
.the_some_struct(
Some_pkg::some_struct_t'{
foo: 1
}))
the_sub ();

endmodule

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