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Internals: Remove m_pkgp and m_classp from WidthVisitor (verilator#4402)
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,9 +1,7 @@ | ||
| %Error: t/t_randomize_method_nclass_bad.v:9:7: Calling implicit class method 'randomize' without being under class | ||
| : ... In instance t | ||
| 9 | randomize(1); | ||
| | ^~~~~~~~~ | ||
| %Error: t/t_randomize_method_nclass_bad.v:10:7: Calling implicit class method 'srandom' without being under class | ||
| : ... In instance t | ||
| 10 | srandom(1); | ||
| | ^~~~~~~ | ||
| %Error: Exiting due to |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,16 @@ | ||
| #!/usr/bin/env perl | ||
| if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } | ||
| # DESCRIPTION: Verilator: Verilog Test driver/expect definition | ||
| # | ||
| # Copyright 2023 by Wilson Snyder. This program is free software; you | ||
| # can redistribute it and/or modify it under the terms of either the GNU | ||
| # Lesser General Public License Version 3 or the Perl Artistic License | ||
| # Version 2.0. | ||
| # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 | ||
|
|
||
| scenarios(simulator => 1); | ||
|
|
||
| compile(); | ||
|
|
||
| ok(1); | ||
| 1; |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,50 @@ | ||
| // DESCRIPTION: Verilator: Verilog Test module | ||
| // | ||
| // This file ONLY is placed under the Creative Commons Public Domain, for | ||
| // any use, without warranty, 2023 by Antmicro Ltd. | ||
| // SPDX-License-Identifier: CC0-1.0 | ||
|
|
||
| typedef class Cls; | ||
|
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||
| class A; | ||
| extern function void method(); | ||
| endclass | ||
|
|
||
| class B; | ||
| extern function void method(); | ||
| endclass | ||
|
|
||
| class C; | ||
| extern function void method(); | ||
| endclass | ||
|
|
||
| class D; | ||
| extern function void method(); | ||
| endclass | ||
|
|
||
| function void A::method(); | ||
| B obj = new; | ||
| obj.method(); | ||
| endfunction | ||
|
|
||
| function void B::method(); | ||
| this.srandom(0); | ||
| endfunction | ||
|
|
||
| function void C::method(); | ||
| this.srandom(0); | ||
| endfunction | ||
|
|
||
| function void D::method(); | ||
| C obj = new; | ||
| obj.method(); | ||
| endfunction | ||
|
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||
| module t; | ||
| A obj1 = new; | ||
| D obj2 = new; | ||
| initial begin | ||
| obj1.method(); | ||
| obj2.method(); | ||
| end | ||
| endmodule |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,24 @@ | ||
| #!/usr/bin/env perl | ||
| if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } | ||
| # DESCRIPTION: Verilator: Verilog Test driver/expect definition | ||
| # | ||
| # Copyright 2023 by Wilson Snyder. This program is free software; you | ||
| # can redistribute it and/or modify it under the terms of either the GNU | ||
| # Lesser General Public License Version 3 or the Perl Artistic License | ||
| # Version 2.0. | ||
| # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 | ||
|
|
||
| scenarios(simulator => 1); | ||
|
|
||
| lint( | ||
| verilator_flags2 => ["--exe --main --timing"], | ||
| make_main => 0, | ||
| ); | ||
|
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||
| lint( | ||
| verilator_flags2 => ["--exe --main --timing --DUSE_STD_PREFIX"], | ||
| make_main => 0, | ||
| ); | ||
|
|
||
| ok(1); | ||
| 1; |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,24 @@ | ||
| // DESCRIPTION: Verilator: Verilog Test module | ||
| // | ||
| // This file ONLY is placed under the Creative Commons Public Domain, for | ||
| // any use, without warranty, 2023 by Antmicro Ltd. | ||
| // SPDX-License-Identifier: CC0-1.0 | ||
|
|
||
| class Foo; | ||
| static task do_something(); | ||
| `ifdef USE_STD_PREFIX | ||
| std::process p; | ||
| `else | ||
| process p; | ||
| `endif | ||
| p = process::self(); | ||
| endtask | ||
| endclass | ||
|
|
||
| module t(); | ||
| initial begin | ||
| Foo::do_something(); | ||
| $write("*-* All Finished *-*\n"); | ||
| $finish; | ||
| end | ||
| endmodule |