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[VeriblePreProcessor][5]: White-spaces support in "VerilogPreprocess" class. #1376

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[VeriblePreProcessor][5]: White-spaces support in "VerilogPreprocess" class. #1376

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NOTE: This is a part of the sequentially splitted PRs from PR #1360.

Description:

  • The preprocessor tool preserves the white-spaces in the SV files.
  • Changed the output of the -generate_variants and -multipe_cu from tokens (enum, text) into normal text.

@karimtera
verible standalone preprocessor: multiple-cu mode [WIP]
24a9b7c
@karimtera
constructing the control flow tree, to enable the preprocessor tool t…
42db6ab 
…o generate all variants with the new mode generate-variants
@karimtera
applying clang-format
ebd1e49
@karimtera
fixing misc. errors in flow_tree.cc
392c605
@karimtera
using ABSL flags in preprocessor tool, edited the tool test just to p…
31d1bb6 
…ass for the moment.
@karimtera
adding usefull comments to flow_tree.cc
a7c5f16
@karimtera
Adding a new common util class.
52856a4 
"verible::CmdPositionalArguments" class only supports these types so far: SV files, +define+<name>[=<value>], and +incdir+<dir>.
@karimtera
fixing clang-tidy errors
325ae9b
@karimtera
Changes:
6c82797 
- Adding an interface function "AddDefineFromCmdLine" to use the macro added by +define+<foo> argument to "VerilogPreprocess".
@karimtera
Changes done:
af28b7f 
- Added a feature to VerilogPreprocess which allows to store paths,
  That can be used later to find the SV file to include.
- The preprocessor tool takes these paths from the user,
  as a +incdir+<path>[+<another_path>] and set then in VerilogPreprocess.
- The included files macros and conditionals can be expanded and evaluated.
- Some limitations exists and were written as TODOs in place,
  need to open issues for these.
@karimtera
Changes done:
8c37dec 
- The preprocessor tool preserves the white-spaces in the SV files.
- Changed the output of the -generate_variants and -multipecu from tokens (enum,text) into normal text.
@karimtera
using run-clang-format.sh
48abc7b
@karimtera karimtera changed the title Pp whitespaces support [VeriblePreProcessor][5]: White-spaces support in "VerilogPreprocess" class. Aug 4, 2022
@karimtera karimtera mentioned this pull request Sep 1, 2022
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@hzeller hzeller mentioned this pull request Feb 21, 2023
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@hzeller hzeller requested a review from kbieganski May 18, 2023 17:32
@hzeller
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hzeller commented May 18, 2023

@kbieganski : this is a pull request that @karimtera started in the GSoC time.
Since you're now taking a closer look at the preprocessor, can you have a look at this, revive and finish ?

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@kbieganski kbieganski Awaiting requested review from kbieganski

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@karimtera @hzeller