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remove EnhancedChisel3Assign in AXI4Xbar #3432

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remove EnhancedChisel3Assign in AXI4Xbar #3432

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5 changes: 2 additions & 3 deletions src/main/scala/amba/axi4/Xbar.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,6 @@ import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import freechips.rocketchip.unittest._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util.EnhancedChisel3Assign

/**
* AXI4 Crossbar. It connects multiple AXI4 masters to slaves.
Expand Down Expand Up @@ -86,7 +85,7 @@ class AXI4Xbar(
// Transform input bundles
val in = Wire(Vec(io_in.size, new AXI4Bundle(wide_bundle)))
for (i <- 0 until in.size) {
in(i) :<> io_in(i)
in(i) :<>= io_in(i)

// Handle size = 1 gracefully (Chisel3 empty range is broken)
def trim(id: UInt, size: Int) = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)
Expand Down Expand Up @@ -169,7 +168,7 @@ class AXI4Xbar(
// Transform output bundles
val out = Wire(Vec(io_out.size, new AXI4Bundle(wide_bundle)))
for (i <- 0 until out.size) {
io_out(i) :<> out(i)
io_out(i) :<>= out(i)

if (io_in.size > 1) {
// Block AW if we cannot record the W source
Expand Down
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