Skip to content
This repository has been archived by the owner on Aug 20, 2024. It is now read-only.

Issues: chipsalliance/firrtl

176 Open 484 Closed
176 Open 484 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Assignee
Filter by who’s assigned
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Issues list

firrtl internal error- caused by java
#2691 opened Jun 12, 2024 by Prasanthyg
3
Internal Error when using the loadMemoryFromFileInline
#2649 opened Jul 19, 2023 by xlgforever
5 tasks done
Firrtl internal exception for adding LoadMemoryFromFile in generators/rocket-chip/src/main/scala/amba/axi4/SRAM.scala
#2634 opened Apr 27, 2023 by chithize
semantics of multi clock memory
#2612 opened Mar 15, 2023 by wky17
How to add options while using treadle to make random validif answer?
#2611 opened Mar 14, 2023 by wky17
2
Internal error - Crash
#2583 opened Dec 7, 2022 by sviraaj
1
DeadCodeElimination transform is not working properly.
#2562 opened Oct 14, 2022 by poddar92
PathNotFoundException in CheckCombLoops transform
#2547 opened Aug 28, 2022 by tymcauley
5 tasks done
Unsupported platform: protoc-3.5.1-osx-aarch_64.exe
#2539 opened Aug 10, 2022 by ilongshan
5 tasks done
4
syntax error(s) when parsing low Firrtl
#2537 opened Aug 6, 2022 by wky17
Dedup causes extra instances to be inlined
#2498 opened Mar 18, 2022 by youngar
3 of 5 tasks
Internal error when loading masked memory from file
#2492 opened Mar 12, 2022 by zyedidia
5 tasks done
1
Internal error when running test
#2484 opened Feb 27, 2022 by hutch31
1
scala.MatchError when using AttributeAnnotation for a module with several instances
#2479 opened Feb 8, 2022 by AlexMontgomerie
1
Add Compiler Build Information to Output Verilog
#2461 opened Jan 14, 2022 by seldridge
1
Extmodule port name check fails with length-parameterized Vec ports
#2437 opened Dec 9, 2021 by johnsbrew
5 tasks done
1
2
RemoveResets Doesn't Look Through Nodes
#2435 opened Dec 7, 2021 by seldridge
Missing Constant Folders
#2432 opened Dec 3, 2021 by seldridge
7 tasks
1
feature request: strength reduction for division or remainder when the denominator is a constant power of two
#2411 opened Nov 10, 2021 by ekiwi
feature request: constant folding for division and remainder
#2410 opened Nov 10, 2021 by ekiwi
1
[RFC] new cover-values statement to efficiently count mutually-exclusive events Feature Request
#2395 opened Oct 25, 2021 by ekiwi
2 tasks done
@seldridge @jackkoenig
4
Optimized Low Firrtl Emitter should not emit skip statements
#2388 opened Oct 15, 2021 by ekiwi
3 tasks
@jackkoenig
Add option to ignore undeserializable annotations (basically pass them through)
#2384 opened Oct 11, 2021 by jackkoenig
3 tasks
@chick
2
Abstract Reset in Uninstantiated Module Crashes without DCE bug
#2373 opened Sep 28, 2021 by seldridge
Verilog Emitter: randomize registers by default
#2366 opened Sep 23, 2021 by ekiwi 1.5.0
@jackkoenig
ProTip! Add no:assignee to see everything that’s not assigned.