"spectrum" example for FOMU (ice40)

.github/scripts/build-examples.sh

@@ -91,6 +91,14 @@ case "$fpga_family" in
     esac
   done
   ;;
+  ice40) for example in $examples; do
+    case $example in
+      "spectrum") tuttest_exec ${snippets} ice40/spectrum/README.rst:ice40-spectrum ;;
+      *) echo "ERROR: Unknown example name: $example" >&2
+        exit 1 ;;
+    esac
+  done
+  ;;
   *) echo "ERROR: Unknown fpga_family: $fpga_family" >&2
     exit 1
   ;;

.github/scripts/generate_job_matrices.py

@@ -105,6 +105,16 @@ def get_jobs(
         'surelog': "-parse -DSYNTHESIS" if usesSurelog else ""
     } for osver in osvers])
 
+    jobs.extend([{
+        'name': "Surelog" if usesSurelog else "Default",
+        'runs-on': runs_on,
+        'fpga-fam': "ice40",
+        'os': osver[0],
+        'os-version': osver[1],
+        'example': "spectrum",
+        'surelog': "-parse -DSYNTHESIS" if usesSurelog else ""
+    } for osver in osvers])
+
     return jobs
 
 for distribution in ['debian', 'ubuntu', 'fedora', 'centos']:

docs/building-examples.rst

@@ -20,14 +20,21 @@ Select your FPGA family:
       .. code-block:: bash
          :name: fpga-fam-xc7
 
-         FPGA_FAM="xc7"
+         export FPGA_FAM=xc7
 
    .. group-tab:: EOS S3
 
       .. code-block:: bash
          :name: fpga-fam-eos-s3
 
-         FPGA_FAM="eos-s3"
+         export FPGA_FAM=eos-s3
+
+   .. group-tab:: ICE40
+
+      .. code-block:: bash
+         :name: fpga-fam-ice40
+
+         export FPGA_FAM=ice40
 
 Next, prepare the environment:
 
@@ -104,3 +111,15 @@ Enter the directory that contains examples for QuickLogic EOS S3:
 
 .. jinja:: eos-s3_btn_counter
    :file: templates/example.jinja
+
+
+Lattice ICE40
+=============
+
+.. code-block:: bash
+   :name: enter-dir-ice40
+
+   cd ice40
+
+.. jinja:: ice40-spectrum
+   :file: templates/example.jinja

docs/getting.rst

@@ -107,6 +107,13 @@ Select your target FPGA family:
 
          export FPGA_FAM=eos-s3
 
+   .. group-tab:: ICE40
+
+      .. code-block:: bash
+         :name: fpga-fam-ice40
+
+         export FPGA_FAM=ice40
+
 Next, setup Conda and your system's environment, and download architecture definitions:
 
 .. NOTE::
@@ -146,6 +153,7 @@ If the above commands exited without errors, you have successfully installed and
 
   * Subdir :ghsrc:`xc7` for the Artix-7 devices
   * Subdir :ghsrc:`eos-s3` for the EOS S3 devices
+  * Subdir :ghsrc:`ice40` for the ICE40 devices
 
 Bumping specific tools
 ======================

ice40/environment.yml

@@ -0,0 +1,31 @@
+# Copyright (C) 2020-2022 F4PGA Authors.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+name: ice40
+
+channels:
+  - litex-hub
+
+dependencies:
+  - litex-hub::yosys=0.15_51_g6318db615=20220317_162926_py37
+  - litex-hub::symbiflow-yosys-plugins=1.0.0_7_832_ga2a80a1=20220317_162926
+  - litex-hub::vtr-optimized=8.0.0_5338_g829c06d8f=20220409_131122
+  - make
+  - git
+  - pip
+  # Packages installed from PyPI
+  - pip:
+    - -r requirements.txt

ice40/requirements.txt

@@ -0,0 +1,17 @@
+# Copyright (C) 2020-2022 F4PGA Authors.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+https://github.com/chipsalliance/f4pga/archive/main.zip#subdirectory=f4pga

ice40/spectrum/Makefile

@@ -0,0 +1,2 @@
+all:
+	f4pga -vvv build --flow ./flow.json

ice40/spectrum/README.rst

@@ -0,0 +1,7 @@
+Spectrum
+~~~~~~~~
+
+.. code-block:: bash
+   :name: ice40-spectrum
+
+   make -C spectrum

ice40/spectrum/flow.json

@@ -0,0 +1,20 @@
+{
+    "default_part": "ICE40UP5K-UWG30",
+    "values": {
+        "top": "top"
+    },
+    "dependencies": {
+        "sources": [
+            "spectrum.v"
+        ],
+        "yosys_synth_log": "synth.log",
+        "nextpnr_pnr_log": "nextpnr.log"
+    },
+    "ICE40UP5K-UWG30": {
+        "default_target": "bitstream",
+        "dependencies": {
+            "build_dir": "build/fomu",
+            "pcf": "fomu.pcf"
+        }
+    }
+}

ice40/spectrum/fomu.pcf

@@ -0,0 +1,4 @@
+set_io led[0] C5
+set_io led[1] B5
+set_io led[2] A5
+set_io clk    F4

ice40/spectrum/spectrum.v

@@ -0,0 +1,114 @@
+/* Spectrum
+ *
+ * This example consists of a series of triangle wave generator with their phases shifted
+ * driving a multichannel PWM generator. The output is supposed to be used to drive LEDs,
+ * which will create a spectrum-like effect.
+ */
+
+module Counter (
+  input  wire clk,
+  output wire [(RESOLUTION-1):0] out
+);
+  parameter RESOLUTION = 4;
+  parameter PHASE = 0;
+  parameter CEILING = (2**RESOLUTION)-1;
+
+  reg [(RESOLUTION-1):0] counter = PHASE;
+
+  always @(posedge clk) begin
+    counter <= (counter == CEILING - 1) ? 0 : (counter + 1);
+  end
+
+  assign out = counter;
+endmodule
+
+module PWMController (
+  input  wire clk,
+  input  wire [(CHANNELS*RESOLUTION-1):0] fill,
+  output wire [(CHANNELS-1):0] out
+);
+  parameter RESOLUTION = 4;
+  parameter CHANNELS = 1;
+
+  reg [(RESOLUTION-1):0] counter = 0;
+
+  always @(posedge clk) begin
+    counter <= counter + 1;
+  end
+
+  genvar i;
+  generate
+  for (i = 0; i < CHANNELS; i++) begin
+    assign out[i] = counter < fill[((i+1)*RESOLUTION-1):(i*RESOLUTION)];
+  end
+  endgenerate
+endmodule
+
+module TriGen (
+  input  wire clk,
+  input  wire [(RESOLUTION):0] ceiling,
+  output wire [(RESOLUTION-1):0] out
+);
+  parameter RESOLUTION = 4;
+  parameter PHASE = 0;
+  parameter CEILING = 2**RESOLUTION;
+
+  wire [RESOLUTION:0] counter_out;
+
+  Counter #(
+    .RESOLUTION  (RESOLUTION+1),
+    .PHASE       (PHASE)
+  ) counter (
+    .clk  (clk),
+    .out  (counter_out)
+  );
+
+  wire [RESOLUTION:0] out_wide;
+
+  assign out_wide = counter_out >= CEILING
+    ? ((~counter_out)+1)
+    : counter_out;
+
+  assign out = out_wide[RESOLUTION:1];
+endmodule
+
+module top (
+  input clk,
+  output [(BITS-1):0] led
+);
+
+  localparam BITS = 3;
+  localparam LOG2DELAY = 18;
+
+  wire [(BITS-1):0] ledctl;
+  wire [(BITS*8-1):0] ledfills;
+
+  genvar i;
+  generate
+    for (i = 0; i < BITS; i++) begin
+
+      wire [8+LOG2DELAY-1:0] trigen_out;
+
+      TriGen #(
+        .RESOLUTION  (8+LOG2DELAY),
+        .PHASE       (i*((2**8)/BITS)*(2**LOG2DELAY))
+      ) trigen (
+        .clk  (clk),
+        .out  (trigen_out)
+      );
+
+      assign ledfills[((i+1)*8-1):(i*8)] = trigen_out >> LOG2DELAY;
+    end
+  endgenerate
+
+  PWMController #(
+    .RESOLUTION  (8),
+    .CHANNELS    (BITS)
+  ) pwm (
+    .clk   (clk),
+    .fill  (ledfills),
+    .out   (ledctl)
+  );
+
+  assign led = ~ledctl;
+endmodule