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Width mismatch lint fixes
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@calebofearth
calebofearth committed Sep 24, 2024
1 parent 49bf6ca commit 9a09f8f
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Showing 3 changed files with 21 additions and 15 deletions.
32 changes: 19 additions & 13 deletions src/axi/rtl/axi_dma_ctrl.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -152,8 +152,8 @@ import soc_ifc_pkg::*;
logic [DW-1:0] r_data_mask;

logic [AW-1:0] src_addr, dst_addr;
logic [$clog2(FIFO_BC/BC+1)-1:0] rd_credits;
logic [$clog2(FIFO_BC/BC+1)-1:0] wr_credits;
logic [FIFO_BW-1:0] rd_credits;
logic [FIFO_BW-1:0] wr_credits;
logic [AXI_LEN_BC_WIDTH-1:0] block_size_mask;
// 1's based counters
logic [31:0] rd_bytes_requested;
Expand Down Expand Up @@ -266,7 +266,7 @@ import soc_ifc_pkg::*;
// Command Decode //
// --------------------------------------- //
generate
if (AW < 32) begin
if (AW <= 32) begin
always_comb begin
src_addr = hwif_out.src_addr_l.addr_l.value[AW-1:0];
dst_addr = hwif_out.dst_addr_l.addr_l.value[AW-1:0];
Expand Down Expand Up @@ -458,27 +458,27 @@ import soc_ifc_pkg::*;

always_comb block_size_mask = hwif_out.block_size.size.value - 1;
always_comb begin
rd_align_req_byte_count = (~|hwif_out.block_size.size.value || (MAX_BLOCK_SIZE < hwif_out.block_size.size.value)) ? (MAX_BLOCK_SIZE - r_req_if.addr[$clog2(MAX_BLOCK_SIZE)-1:0]) :
hwif_out.block_size.size.value - (r_req_if.addr[$clog2(MAX_BLOCK_SIZE)-1:0] & block_size_mask);
rd_align_req_byte_count = (~|hwif_out.block_size.size.value || (MAX_BLOCK_SIZE < hwif_out.block_size.size.value)) ? AXI_LEN_BC_WIDTH'(MAX_BLOCK_SIZE - r_req_if.addr[$clog2(MAX_BLOCK_SIZE)-1:0]) :
AXI_LEN_BC_WIDTH'(hwif_out.block_size.size.value - (AXI_LEN_BC_WIDTH'(r_req_if.addr[$clog2(MAX_BLOCK_SIZE)-1:0]) & block_size_mask));
rd_final_req_byte_count = rd_bytes_rem_thresh ? AXI_LEN_BC_WIDTH'(hwif_out.byte_count.count.value - rd_bytes_requested) :
{AXI_LEN_BC_WIDTH{1'b1}};
rd_req_byte_count = rd_final_req_byte_count < rd_align_req_byte_count ? rd_final_req_byte_count :
rd_align_req_byte_count;
wr_align_req_byte_count = (~|hwif_out.block_size.size.value || (MAX_BLOCK_SIZE < hwif_out.block_size.size.value)) ? (MAX_BLOCK_SIZE - w_req_if.addr[$clog2(MAX_BLOCK_SIZE)-1:0]) :
hwif_out.block_size.size.value - (w_req_if.addr[$clog2(MAX_BLOCK_SIZE)-1:0] & block_size_mask);
wr_align_req_byte_count = (~|hwif_out.block_size.size.value || (MAX_BLOCK_SIZE < hwif_out.block_size.size.value)) ? AXI_LEN_BC_WIDTH'(MAX_BLOCK_SIZE - w_req_if.addr[$clog2(MAX_BLOCK_SIZE)-1:0]) :
AXI_LEN_BC_WIDTH'(hwif_out.block_size.size.value - (AXI_LEN_BC_WIDTH'(w_req_if.addr[$clog2(MAX_BLOCK_SIZE)-1:0]) & block_size_mask));
wr_final_req_byte_count = wr_bytes_rem_thresh ? AXI_LEN_BC_WIDTH'(hwif_out.byte_count.count.value - wr_bytes_requested) :
{AXI_LEN_BC_WIDTH{1'b1}};
wr_req_byte_count = wr_final_req_byte_count < wr_align_req_byte_count ? wr_final_req_byte_count :
wr_align_req_byte_count;
end

always_comb begin
r_req_if.valid = (ctrl_fsm_ps == DMA_WAIT_DATA) && !rd_req_hshake_bypass && (rd_bytes_requested < hwif_out.byte_count.count.value) && (rd_credits >= rd_req_byte_count[AXI_LEN_BC_WIDTH-1:BW]) && !rd_req_stall;
r_req_if.valid = (ctrl_fsm_ps == DMA_WAIT_DATA) && !rd_req_hshake_bypass && (rd_bytes_requested < hwif_out.byte_count.count.value) && ((AXI_LEN_BC_WIDTH-BW)'(rd_credits) >= rd_req_byte_count[AXI_LEN_BC_WIDTH-1:BW]) && !rd_req_stall;
r_req_if.addr = src_addr + rd_bytes_requested;
r_req_if.byte_len = rd_req_byte_count - AXI_LEN_BC_WIDTH'(BC);
r_req_if.fixed = hwif_out.ctrl.rd_fixed.value;
r_req_if.lock = 1'b0; // TODO
w_req_if.valid = (ctrl_fsm_ps == DMA_WAIT_DATA) && !wr_req_hshake_bypass && (wr_bytes_requested < hwif_out.byte_count.count.value) && (wr_credits >= wr_req_byte_count[AXI_LEN_BC_WIDTH-1:BW]);
w_req_if.valid = (ctrl_fsm_ps == DMA_WAIT_DATA) && !wr_req_hshake_bypass && (wr_bytes_requested < hwif_out.byte_count.count.value) && ((AXI_LEN_BC_WIDTH-BW)'(wr_credits) >= wr_req_byte_count[AXI_LEN_BC_WIDTH-1:BW]);
w_req_if.addr = dst_addr + wr_bytes_requested;
w_req_if.byte_len = wr_req_byte_count - AXI_LEN_BC_WIDTH'(BC);
w_req_if.fixed = hwif_out.ctrl.wr_fixed.value;
Expand Down Expand Up @@ -555,11 +555,13 @@ import soc_ifc_pkg::*;
else if ((ctrl_fsm_ps == DMA_IDLE) || (rd_req_hshake_bypass)) begin
rd_credits <= FIFO_BC/BC;
end
// Request byte count is restricted to not exceed the credit capacity
// Assertions (below) enforce a legal byte_count for sims
else if (rd_req_hshake && (fifo_r_valid && fifo_r_ready)) begin
rd_credits <= rd_credits + 1 - rd_req_byte_count[AXI_LEN_BC_WIDTH-1:BW];
rd_credits <= rd_credits + 1 - FIFO_BW'(rd_req_byte_count[AXI_LEN_BC_WIDTH-1:BW]);
end
else if (rd_req_hshake) begin
rd_credits <= rd_credits - rd_req_byte_count[AXI_LEN_BC_WIDTH-1:BW];
rd_credits <= rd_credits - FIFO_BW'(rd_req_byte_count[AXI_LEN_BC_WIDTH-1:BW]);
end
else if (fifo_r_valid && fifo_r_ready) begin
rd_credits <= rd_credits + 1;
Expand All @@ -573,11 +575,13 @@ import soc_ifc_pkg::*;
else if ((ctrl_fsm_ps == DMA_IDLE) || (wr_req_hshake_bypass)) begin
wr_credits <= 0;
end
// Request byte count is restricted to not exceed the credit capacity
// Assertions (below) enforce a legal byte_count for sims
else if (wr_req_hshake && (fifo_w_valid && fifo_w_ready)) begin
wr_credits <= wr_credits + 1 - wr_req_byte_count[AXI_LEN_BC_WIDTH-1:BW];
wr_credits <= wr_credits + 1 - FIFO_BW'(wr_req_byte_count[AXI_LEN_BC_WIDTH-1:BW]);
end
else if (wr_req_hshake) begin
wr_credits <= wr_credits - wr_req_byte_count[AXI_LEN_BC_WIDTH-1:BW];
wr_credits <= wr_credits - FIFO_BW'(wr_req_byte_count[AXI_LEN_BC_WIDTH-1:BW]);
end
else if (fifo_w_valid && fifo_w_ready) begin
wr_credits <= wr_credits + 1;
Expand Down Expand Up @@ -712,9 +716,11 @@ import soc_ifc_pkg::*;
`CALIPTRA_ASSERT_INIT(AXI_DMA_DW_EQ_MB, DW == MBOX_DATA_W)
// FIFO must have space for all requested data
`CALIPTRA_ASSERT(AXI_DMA_LIM_RD_CRED, rd_credits <= FIFO_BC/BC, clk, !rst_n)
`CALIPTRA_ASSERT(AXI_DMA_OFL_RD_CRED, rd_req_hshake |-> rd_req_byte_count <= FIFO_BC, clk, !rst_n)
`CALIPTRA_ASSERT(AXI_DMA_MIN_RD_CRED, !((rd_credits < BC) && rd_req_hshake), clk, !rst_n)
`CALIPTRA_ASSERT(AXI_DMA_RST_RD_CRED, (ctrl_fsm_ps == DMA_DONE) |-> (rd_credits == FIFO_BC/BC), clk, !rst_n)
`CALIPTRA_ASSERT(AXI_DMA_LIM_WR_CRED, wr_credits <= FIFO_BC/BC, clk, !rst_n)
`CALIPTRA_ASSERT(AXI_DMA_UFL_WR_CRED, wr_req_hshake |-> wr_credits >= wr_req_byte_count[AXI_LEN_BC_WIDTH-1:BW], clk, !rst_n)
`CALIPTRA_ASSERT(AXI_DMA_MIN_WR_CRED, !((wr_credits < BC) && wr_req_hshake), clk, !rst_n)
`CALIPTRA_ASSERT(AXI_DMA_RST_WR_CRED, (ctrl_fsm_ps == DMA_DONE) |-> (wr_credits == 0), clk, !rst_n)

Expand Down
2 changes: 1 addition & 1 deletion src/axi/rtl/axi_sub_rd.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -150,7 +150,7 @@ module axi_sub_rd import axi_pkg::*; #(
txn_cnt <= '0;
end
else if (s_axi_if.arvalid && s_axi_if.arready) begin
txn_ctx.addr <= s_axi_if.araddr;
txn_ctx.addr <= s_axi_if.araddr[AW-1:0];
txn_ctx.burst <= axi_burst_e'(s_axi_if.arburst);
txn_ctx.size <= s_axi_if.arsize;
txn_ctx.len <= s_axi_if.arlen ;
Expand Down
2 changes: 1 addition & 1 deletion src/axi/rtl/axi_sub_wr.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -122,7 +122,7 @@ module axi_sub_wr import axi_pkg::*; #(
// --------------------------------------- //

always_comb begin
s_axi_if_ctx.addr = s_axi_if.awaddr ;
s_axi_if_ctx.addr = s_axi_if.awaddr[AW-1:0] ;
s_axi_if_ctx.burst = axi_burst_e'(s_axi_if.awburst);
s_axi_if_ctx.size = s_axi_if.awsize ;
s_axi_if_ctx.len = s_axi_if.awlen ;
Expand Down

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