SweRVolf 0.7

SweRV EH1 1.6

The SweRV EH1 CPU has been upgraded to version 1.6. See the SweRV EH1 release notes for more information

Reenabled icache

An updated OpenOCD now supports the SweRV instruction cache, which is now reenabled by default. Make sure to use the latest version of OpenOCD

Software interrupts support

New registers have been added to the system controller to allow triggering external interrrupts as well as the NMI. A new timer has been added as well to allow triggering delayed interrupts, e.g. to test wake-up functionality.

Update AXI components

The AXI interconnect and CDC has been updated to newer versions, which are more robust and performant.

Wishbone subsystem

Related to the updated AXI infrastructure, all peripheral controllers and boot ROM has been moved to a separate Wishbone subsystem which is connected to a slave port on the main AXI interconnect. This makes it easier to add more Wishbone-compatible components in the future.

Support for Riviera-PRO

Aldec Riviera-PRO is now a supported simulator, together with QuestaSim, Verilator and VCS. Other simulators supported by Edalize have a good chance of working too (e.g. xcelium) but are not officially supported.

RISCV-compliance compatibility

Updates have been made to the riscv-target files to support the lastest version of the RISC-V compliance test suite

Improved instructions

The project setup instructions have been simplified and changed for correctness

Updated DDR2 controller

The DDR2 controller, generated by LiteDRAM, has been updated and now uses SERV instead of VexRiscV internally to save resources