SweRVolf 0.6

SweRV EH1 1.5

The SweRV EH1 CPU has been upgraded to version 1.5. See the SweRV EH1 release notes for more information

Disabled icache

To work around an issue with gdb, the default SweRVolf configuration is built with out instruction cache. To enable the instruction cache or change other CPU features, change the corresponding options in the core description file and rebuild

Nexys A7 LEDs and switches mapped to GPIO

The GPIO controller has been expanded and the 16 LEDS and switches are mapped to GPIO. See the documentation for more information. The default demo application is also updated to take advantage of the new GPIO

VCS compatibility

A VCS-incompatible issue was found in one of the dependencies of SweRVolf. This has been fixed and the dependency has been updated so that simulations should work with VCS in addition to the officially support of Questasim and Verilator

mtimecmp is readable

A bug that prevented reading back mtimecmp was found and fixed

Unified bootloader

A new unified bootloader replaces the three previous bootloaders. This allows changing the boot mode by setting GPIO in different positions during power-on. See the documentation for more info

Testbench runs at 50MHz

The verilog testbench was wrongly set to simulate a 25MHz clock which was inconsistent with the provided software, which assumes 50MHz for correct UART baud rate and timer tick frequency