Add Zephyr support for SPI Flash

chipsalliance · Jan 9, 2020 · 30b22c1 · 30b22c1
1 parent d4d0c5d
commit 30b22c1
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diff --git a/zephyr/boards/riscv/swervolf_nexys/Kconfig.defconfig b/zephyr/boards/riscv/swervolf_nexys/Kconfig.defconfig
@@ -3,4 +3,11 @@ if BOARD_SWERVOLF_NEXYS
 config BOARD
 	default "swervolf_nexys"
 
+if FLASH
+
+config SPI_NOR
+	def_bool y
+
+endif
+
 endif
diff --git a/zephyr/boards/riscv/swervolf_nexys/swervolf_nexys.dts b/zephyr/boards/riscv/swervolf_nexys/swervolf_nexys.dts
@@ -29,3 +29,15 @@
 	clock-frequency = <50000000>;
 };
 
+&spi0 {
+	status = "okay";
+
+	flash0: flash@0 {
+		compatible = "jedec,spi-nor";
+		label = "FLASH0";
+		jedec-id = [01 20 18];
+		size = <0x1000000>;
+		reg = <0>;
+		spi-max-frequency = <2000000>;
+	};
+};
diff --git a/zephyr/dts/riscv/riscv32-swerv.dtsi b/zephyr/dts/riscv/riscv32-swerv.dtsi
@@ -45,5 +45,15 @@
 			interrupts = <12 15>;
 			status = "disabled";
 		};
+
+		spi0: spi@80001040 {
+			compatible = "opencores,spi-simple";
+			reg = <0x80001040 0x40>;
+			reg-names = "control";
+			label = "SPI0";
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
 	};
 };
diff --git a/zephyr/soc/riscv/swervolf/Kconfig.defconfig b/zephyr/soc/riscv/swervolf/Kconfig.defconfig
@@ -38,6 +38,16 @@ config GPIO_MMIO32
 
 endif # GPIO
 
+if SPI
+
+config SPI_OC_SIMPLE
+	def_bool y
+
+config SPI_OC_SIMPLE_BUS_WIDTH
+	def_int 64
+
+endif # SPI
+
 config XIP
 	def_bool n