Tidy/reflow some things

docs/source/appendix/APPNOTE_010_Verilog_to_BLIF.rst

@@ -189,13 +189,13 @@ values for the global asynchronous reset in an FPGA implementation. This design
 can not be expressed in BLIF as it is. Instead we need to use a synthesis script
 that transforms this form to synchronous resets that can be expressed in BLIF.
 
-(Note that there is no problem if this coding techniques are used to
-model ROM, where the register is initialized using this syntax but is
-never updated otherwise.)
+(Note that there is no problem if this coding techniques are used to model ROM,
+where the register is initialized using this syntax but is never updated
+otherwise.)
 
 :numref:`amber23.ys` shows the synthesis script for the Amber23 core. In line 17
 the add command is used to add a 1-bit wide global input signal with the name
-globrst. That means that an input with that name is added to each module in the
+``globrst``. That means that an input with that name is added to each module in the
 design hierarchy and then all module instantiations are altered so that this new
 signal is connected throughout the whole design hierarchy.
 
@@ -235,18 +235,18 @@ signal is connected throughout the whole design hierarchy.
 
    endmodule
 
-In line 18 the proc command is called. But in this script the signal
-name globrst is passed to the command as a global reset signal for
-resetting the registers to their assigned initial values.
+In line 18 the ``proc`` command is called. But in this script the signal name
+globrst is passed to the command as a global reset signal for resetting the
+registers to their assigned initial values.
 
 Finally in line 19 the techmap command is used to replace all instances of
 flip-flops with asynchronous resets with flip-flops with synchronous resets. The
 map file used for this is shown in :numref:`adff2dff.v`. Note how the
-techmap_celltype attribute is used in line 1 to tell the techmap command which
-cells to replace in the design, how the \_TECHMAP_FAIL\_ wire in lines 15 and 16
-(which evaluates to a constant value) determines if the parameter set is
-compatible with this replacement circuit, and how the \_TECHMAP_DO\_ wire in
-line 13 provides a mini synthesis-script to be used to process this cell.
+``techmap_celltype`` attribute is used in line 1 to tell the techmap command
+which cells to replace in the design, how the ``_TECHMAP_FAIL_`` wire in lines
+15 and 16 (which evaluates to a constant value) determines if the parameter set
+is compatible with this replacement circuit, and how the ``_TECHMAP_DO_`` wire
+in line 13 provides a mini synthesis-script to be used to process this cell.
 
 .. code-block:: c
    :caption: Test program for the Amber23 CPU (Sieve of Eratosthenes). Compiled 
@@ -298,39 +298,36 @@ format as well.
 
 .. _ABC: https://github.com/berkeley-abc/abc
 
-The only thing left to write about the simulation itself is that it
-probably was one of the most energy inefficient and time consuming ways
-of successfully calculating the first 31 primes the author has ever
-conducted.
+The only thing left to write about the simulation itself is that it probably was
+one of the most energy inefficient and time consuming ways of successfully
+calculating the first 31 primes the author has ever conducted.
 
 Limitations
 ===========
 
-At the time of this writing Yosys does not support multi-dimensional
-memories, does not support writing to individual bits of array elements,
-does not support initialization of arrays with $readmemb and $readmemh,
-and has only limited support for tristate logic, to name just a few
-limitations.
+At the time of this writing Yosys does not support multi-dimensional memories,
+does not support writing to individual bits of array elements, does not support
+initialization of arrays with ``$readmemb`` and ``$readmemh``, and has only
+limited support for tristate logic, to name just a few limitations.
 
-That being said, Yosys can synthesize an overwhelming majority of
-real-world Verilog RTL code. The remaining cases can usually be modified
-to be compatible with Yosys quite easily.
+That being said, Yosys can synthesize an overwhelming majority of real-world
+Verilog RTL code. The remaining cases can usually be modified to be compatible
+with Yosys quite easily.
 
-The various designs in yosys-bigsim are a good place to look for
-examples of what is within the capabilities of Yosys.
+The various designs in yosys-bigsim are a good place to look for examples of
+what is within the capabilities of Yosys.
 
 Conclusion
 ==========
 
-Yosys is a feature-rich Verilog-2005 synthesis tool. It has many uses,
-but one is to provide an easy gateway from high-level Verilog code to
-low-level logic circuits.
+Yosys is a feature-rich Verilog-2005 synthesis tool. It has many uses, but one
+is to provide an easy gateway from high-level Verilog code to low-level logic
+circuits.
 
-The command line option -S can be used to quickly synthesize Verilog
-code to BLIF files without a hassle.
+The command line option ``-S`` can be used to quickly synthesize Verilog code to
+BLIF files without a hassle.
 
-With custom synthesis scripts it becomes possible to easily perform
-high-level optimizations, such as re-encoding FSMs. In some extreme
-cases, such as the Amber23 ARMv2 CPU, the more advanced Yosys features
-can be used to change a design to fit a certain need without actually
-touching the RTL code.
+With custom synthesis scripts it becomes possible to easily perform high-level
+optimizations, such as re-encoding FSMs. In some extreme cases, such as the
+Amber23 ARMv2 CPU, the more advanced Yosys features can be used to change a
+design to fit a certain need without actually touching the RTL code.

docs/source/appendix/APPNOTE_011_Design_Investigation.rst

@@ -315,7 +315,7 @@ simply be abbreviated using the last part.
 Usually all interactive work is done with one module selected using the ``cd``
 command. But it is also possible to work from the design-context (``cd ..``). In
 this case all object names must be prefixed with ``<module_name>/``. For example
-``a*/b\*`` would refer to all objects whose names start with ``b`` from all
+``a*/b*`` would refer to all objects whose names start with ``b`` from all
 modules whose names start with ``a``.
 
 The ``dump`` command can be used to print all information about an object. For
@@ -416,7 +416,7 @@ will select all ``$add ``cells that have the ``foo`` attribute set:
 
    select t:$add a:foo %i
 
-The listing in :numref:`sumprod` uses the Yosys non-standard ``{... \*}`` syntax
+The listing in :numref:`sumprod` uses the Yosys non-standard ``{... *}`` syntax
 to set the attribute ``sumstuff`` on all cells generated by the first assign
 statement. (This works on arbitrary large blocks of Verilog code an can be used
 to mark portions of code for analysis.)
@@ -467,7 +467,7 @@ be a bit dull. So there is a shortcut for that: the number of iterations can be
 appended to the action. So for example the action ``%ci3`` is identical to
 performing the ``%ci`` action three times.
 
-The action ``%ci\*`` performs the ``%ci`` action over and over again until it
+The action ``%ci*`` performs the ``%ci`` action over and over again until it
 has no effect anymore.
 
 .. figure:: ../../images/011/select_prod.*

docs/source/appendix/primer.rst

@@ -586,7 +586,7 @@ use the Token-Type to make a decision on the grammatical role of a token.
 
 The parser then transforms the list of tokens into a parse tree that closely
 resembles the productions from the computer languages grammar. As the lexer, the
-parser is also typically generated by a code generator (e.g. bison ) from a
+parser is also typically generated by a code generator (e.g. bison) from a
 grammar description in Backus-Naur Form (BNF).
 
 Let's consider the following BNF (in Bison syntax):

docs/source/getting_started/installation.rst

@@ -43,15 +43,15 @@ directories:
      simulation results of the synthesized design to the original sources to
      logic equivalence checking of entire CPU cores.
 
-The top-level Makefile includes frontends/\*/Makefile.inc,
-passes/\*/Makefile.inc and backends/\*/Makefile.inc. So when extending Yosys it
-is enough to create a new directory in frontends/, passes/ or backends/ with
-your sources and a Makefile.inc. The Yosys kernel automatically detects all
-commands linked with Yosys. So it is not needed to add additional commands to a
-central list of commands.
+The top-level Makefile includes ``frontends/*/Makefile.inc``,
+``passes/*/Makefile.inc`` and ``backends/*/Makefile.inc``. So when extending
+Yosys it is enough to create a new directory in ``frontends/``, ``passes/`` or
+``backends/`` with your sources and a ``Makefile.inc``. The Yosys kernel
+automatically detects all commands linked with Yosys. So it is not needed to add
+additional commands to a central list of commands.
 
 Good starting points for reading example source code to learn how to write
-passes are passes/opt/opt_rmdff.cc and passes/opt/opt_merge.cc.
+passes are ``passes/opt/opt_rmdff.cc`` and ``passes/opt/opt_merge.cc``.
 
 See the top-level README file for a quick Getting Started guide and build
 instructions. The Yosys build is based solely on Makefiles.

docs/source/getting_started/scripting_intro.rst

@@ -99,14 +99,14 @@ Selections intro
 ~~~~~~~~~~~~~~~~
 
 Most commands can operate not only on the entire design but also specifically on
-selected parts of the design. For example the command dump will print all
-selected objects in the current design while dump foobar will only print the
-module foobar and dump \* will print the entire design regardless of the current
-selection.
+selected parts of the design. For example the command ``dump`` will print all
+selected objects in the current design while ``dump foobar`` will only print the
+module ``foobar`` and ``dump *`` will print the entire design regardless of the
+current selection.
 
 .. code:: yoscrypt
 
-	dump */t:$add %x:+[A] \*/w:\* %i
+	dump */t:$add %x:+[A] */w:* %i
 
 The selection mechanism is very powerful. For example the command above will
 print all wires that are connected to the ``\A`` port of a ``$add`` cell.

docs/source/introduction.rst

@@ -50,15 +50,6 @@ What you can do with Yosys
 - Perform all kinds of operations on netlist (RTL, Logic, Gate)
 - Perform logic optimizations and gate mapping with ABC
 
-Things you can't do
-~~~~~~~~~~~~~~~~~~~
-
-- Process high-level languages such as C/C++/SystemC
-- Create physical layouts (place&route)
-  + Check out `nextpnr`_ for that
-
-.. _nextpnr: https://github.com/YosysHQ/nextpnr
-
 Typical applications for Yosys
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
@@ -71,12 +62,21 @@ Typical applications for Yosys
 - Framework for building custom flows (Not limited to synthesis but also formal
   verification, reverse engineering, ...)
 
+Things you can't do
+~~~~~~~~~~~~~~~~~~~
+
+- Process high-level languages such as C/C++/SystemC
+- Create physical layouts (place&route)
+  + Check out `nextpnr`_ for that
+
+.. _nextpnr: https://github.com/YosysHQ/nextpnr
+
 Benefits of open source HDL synthesis
 -------------------------------------
 
 - Cost (also applies to ``free as in free beer`` solutions): 
 
-  Today the cost for a mask set in $\unit[180]{nm}$ technology is far less than
+  Today the cost for a mask set in 180nm technology is far less than
   the cost for the design tools needed to design the mask layouts. Open Source
   ASIC flows are an important enabler for ASIC-level Open Source Hardware.
 

docs/source/using_yosys/more_scripting/opt_passes.rst

@@ -143,7 +143,7 @@ identifies cells with identical inputs and replaces them with a single instance
 of the cell.
 
 The option ``-nomux`` can be used to disable resource sharing for multiplexer
-cells (``$mux`` and ``$pmux.`` This can be useful as it prevents multiplexer
+cells (``$mux`` and ``$pmux``.) This can be useful as it prevents multiplexer
 trees to be merged, which might prevent ``opt_muxtree`` to identify possible
 optimizations.