Merge pull request #3992 from YosysHQ/empty-case-fix

write_verilog: avoid emitting empty cases.
YosysHQ · Oct 8, 2023 · a79b15e · a79b15e
2 parents a1923a5 + c36cf9c
commit a79b15e
Showing 1 changed file with 5 additions and 0 deletions.
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
@@ -2008,6 +2008,11 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw
 		dump_case_body(f, indent + "    ", *it);
 	}
 
+	if (sw->cases.empty()) {
+		// Verilog does not allow empty cases.
+		f << stringf("%s  default: ;\n", indent.c_str());
+	}
+
 	f << stringf("%s" "endcase\n", indent.c_str());
 }