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Correction and optimization of nowrshmsk
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This makes tests/verilog/dynamic_range_lhs.v pass, after ensuring that
nowrshmsk is actually tested.

Stride is extracted from indexing of two-dimensional packed arrays and
variable slices on the form dst[i*stride +: width] = src, and is used
to optimize the generated CASE block.
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daglem committed Nov 15, 2023
1 parent f37ce5c commit 8a925ce
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Showing 2 changed files with 69 additions and 24 deletions.
91 changes: 68 additions & 23 deletions frontends/ast/simplify.cc
Original file line number Diff line number Diff line change
Expand Up @@ -2824,27 +2824,12 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
if (!children[0]->id2ast->range_valid)
goto skip_dynamic_range_lvalue_expansion;

int source_width = children[0]->id2ast->range_left - children[0]->id2ast->range_right + 1;
AST::AstNode *member_node = get_struct_member(children[0]);
int source_width = member_node ?
member_node->range_left - member_node->range_right + 1 :
children[0]->id2ast->range_left - children[0]->id2ast->range_right + 1;
int source_offset = children[0]->id2ast->range_right;
int result_width = 1;
int stride = 1;
AST::AstNode *member_node = get_struct_member(children[0]);
if (member_node) {
// Clamp chunk to range of member within struct/union.
log_assert(!source_offset && !children[0]->id2ast->range_swapped);
source_width = member_node->range_left - member_node->range_right + 1;

// When the (* nowrshmsk *) attribute is set, a CASE block is generated below
// to select the indexed bit slice. When a multirange array is indexed, the
// start of each possible slice is separated by the bit stride of the last
// index dimension, and we can optimize the CASE block accordingly.
// The dimension of the original array expression is saved in the 'integer' field.
int dims = children[0]->integer;
stride = source_width;
for (int dim = 0; dim < dims; dim++) {
stride /= get_struct_range_width(member_node, dim);
}
}

AstNode *shift_expr = NULL;
AstNode *range = children[0]->children[0];
Expand Down Expand Up @@ -2875,12 +2860,72 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
{
// big case block

int stride = 1;
int div_stride = 1;

// Extract (index)*(width) from non_opt_range pattern (@selfsz@((index)*(width)))+(0)).
AstNode *lsb_expr =
shift_expr->type == AST_ADD && shift_expr->children[0]->type == AST_SELFSZ &&
shift_expr->children[1]->type == AST_CONSTANT && shift_expr->children[1]->integer == 0 ?
shift_expr->children[0]->children[0] :
shift_expr;

// Optimization: Extract stride from indexing of two-dimensional packed arrays and
// variable slices on the form dst[i*stride +: width] = src.
// Don't bother optimizing the degenerate case dst[i*0 +: width] = src.
if (!source_offset && lsb_expr->type == AST_MUL &&
((lsb_expr->children[0]->type == AST_CONSTANT && lsb_expr->children[0]->integer) ||
(lsb_expr->children[1]->type == AST_CONSTANT && lsb_expr->children[1]->integer)))
{
int const_i = lsb_expr->children[1]->type == AST_CONSTANT;
stride = (int)lsb_expr->children[const_i]->integer;
if (stride < 0) {
// The CASE block generation below assumes a positive stride.
stride = -stride;
}

// Remove multiplication of index by stride.
// FIXME: Counterintuitively, this can yield higher resource usage. Disable for now.
#if 0
div_stride = stride;
AstNode *tmp = lsb_expr->children[1 - const_i]->clone();
delete shift_expr;
shift_expr = tmp;
#endif
}
else if (member_node) // Member in packed struct/union
{
// Clamp chunk to range of member within struct/union.
log_assert(!source_offset && !children[0]->id2ast->range_swapped);

// When the (* nowrshmsk *) attribute is set, a CASE block is generated below
// to select the indexed bit slice. When a multirange array is indexed, the
// start of each possible slice is separated by the bit stride of the last
// index dimension, and we can optimize the CASE block accordingly.
// The dimension of the original array expression is saved in the 'integer' field.
int dims = children[0]->integer;
stride = source_width;
for (int dim = 0; dim < dims; dim++) {
stride /= get_struct_range_width(member_node, dim);
}
}

// Limit case conditions to possible index range.
int case_width_hint = -1;
bool case_sign_hint = true;
shift_expr->detectSignWidth(case_width_hint, case_sign_hint);
int max_bits = min(case_width_hint, 31 + case_sign_hint);
int max_offset = (1u << (max_bits - case_sign_hint)) - 1;
int min_offset = case_sign_hint ? -(1u << (max_bits - 1)) : 0;

did_something = true;
newNode = new AstNode(AST_CASE, shift_expr);
for (int i = 0; i < source_width; i += stride) {
for (int i = (1 - result_width)/stride*stride; i < source_width; i += stride) {
int start_bit = source_offset + i;
int end_bit = std::min(start_bit+result_width,source_width) - 1;
AstNode *cond = new AstNode(AST_COND, mkconst_int(start_bit, true));
int end_bit = std::min(start_bit + result_width, source_offset + source_width) - 1;
if (start_bit/div_stride < min_offset || start_bit/div_stride > max_offset)
continue;
AstNode *cond = new AstNode(AST_COND, mkconst_int(start_bit/div_stride, case_sign_hint, case_width_hint));
AstNode *lvalue = children[0]->clone();
lvalue->delete_children();
if (member_node)
Expand All @@ -2893,7 +2938,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
}
else
{
// mask and shift operations, disabled for now
// mask and shift operations

AstNode *wire_mask = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(source_width-1, true), mkconst_int(0, true)));
wire_mask->str = stringf("$bitselwrite$mask$%s:%d$%d", RTLIL::encode_filename(filename).c_str(), location.first_line, autoidx++);
Expand Down
2 changes: 1 addition & 1 deletion tests/verilog/dynamic_range_lhs.v
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
module gate(
output reg [`LEFT:`RIGHT] out_u, out_s,
(* nowrshmsk = `ALT *)
output reg [`LEFT:`RIGHT] out_u, out_s,
input wire data,
input wire [1:0] sel1, sel2
);
Expand Down

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