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simlib.v: Add x-output tag
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Also a few extra cell help texts.
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KrystalDelusion committed Sep 6, 2024
1 parent 7f20645 commit 831e108
Showing 1 changed file with 23 additions and 10 deletions.
33 changes: 23 additions & 10 deletions techlibs/common/simlib.v
Original file line number Diff line number Diff line change
Expand Up @@ -506,7 +506,13 @@ endgenerate
endmodule

// --------------------------------------------------------

//* ver 2
//* title Indexed part-select
//* group binary
//* tags x-output
//- Same as the `$shift` cell, but fills with 'x'.
//-

module \$shift (A, B, Y);

Expand Down Expand Up @@ -539,7 +545,13 @@ endgenerate
endmodule

// --------------------------------------------------------

//* ver 2
//* title Variable shifter
//* group binary
//- Performs a right logical shift if the second operand is positive (or
//- unsigned), and a left logical shift if it is negative.
//-

module \$shiftx (A, B, Y);

Expand Down Expand Up @@ -1184,12 +1196,12 @@ endmodule

// --------------------------------------------------------

// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $div (A, B, Y)
//* ver 2
//* title Divider
//* group binary
//-
//- Division with truncated result (rounded towards 0).
//* tags x-output
//- This corresponds to the Verilog '/' operator, performing division and
//- truncating the result (rounding towards 0).
//-
module \$div (A, B, Y);

Expand All @@ -1215,12 +1227,12 @@ endmodule

// --------------------------------------------------------

// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $mod (A, B, Y)
//* ver 2
//* title Modulo
//* group binary
//-
//- Modulo/remainder of division with truncated result (rounded towards 0).
//* tags x-output
//- This corresponds to the Verilog '%' operator, giving the module (or
//- remainder) of division and truncating the result (rounding towards 0).
//-
//- Invariant: $div(A, B) * B + $mod(A, B) == A
//-
Expand Down Expand Up @@ -1541,6 +1553,7 @@ endmodule

// --------------------------------------------------------
//* group mux
//* tags x-output

module \$pmux (A, B, S, Y);

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