Merge pull request #3909 from YosysHQ/widelut

Default nowidelut for xo2/3/3d
YosysHQ · Aug 29, 2023 · 51ddfb1 · 51ddfb1
2 parents 572ad34 + a42c630
commit 51ddfb1
Show file tree

Hide file tree

Showing 4 changed files with 18 additions and 6 deletions.
diff --git a/techlibs/lattice/synth_lattice.cc b/techlibs/lattice/synth_lattice.cc
@@ -102,6 +102,10 @@ struct SynthLatticePass : public ScriptPass
 		log("\n");
 		log("    -nowidelut\n");
 		log("        do not use PFU muxes to implement LUTs larger than LUT4s\n");
+		log("        (by default enabled on MachXO2/XO3/XO3D)\n");
+		log("\n");
+		log("    -widelut\n");
+		log("        force use of PFU muxes to implement LUTs larger than LUT4s\n");
 		log("\n");
 		log("    -asyncprld\n");
 		log("        use async PRLD mode to implement ALDFF (EXPERIMENTAL)\n");
@@ -163,6 +167,7 @@ struct SynthLatticePass : public ScriptPass
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
 		string run_from, run_to;
+		bool force_widelut = false;
 		clear_flags();
 
 		size_t argidx;
@@ -230,6 +235,12 @@ struct SynthLatticePass : public ScriptPass
 			}
 			if (args[argidx] == "-nowidelut" || /*deprecated alias*/ args[argidx] == "-nomux") {
 				nowidelut = true;
+				force_widelut = true;
+				continue;
+			}
+			if (args[argidx] == "-widelut") {
+				nowidelut = false;
+				force_widelut = true;
 				continue;
 			}
 			if (args[argidx] == "-abc2") {
@@ -273,6 +284,7 @@ struct SynthLatticePass : public ScriptPass
 			arith_map = "_ccu2d";
 			brams_map = "_8kc";
 			have_dsp = false;
+			if (!force_widelut) nowidelut = true;
 /*		} else if (family == "xo" ||
 				family == "pm") {
 		} else if (family == "xp" ||

diff --git a/tests/arch/machxo2/fsm.ys b/tests/arch/machxo2/fsm.ys
@@ -3,7 +3,7 @@ hierarchy -top fsm
 proc
 flatten
 
-equiv_opt -run :prove -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 -nowidelut
+equiv_opt -run :prove -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2
 miter -equiv -make_assert -flatten gold gate miter
 sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
 

diff --git a/tests/arch/machxo2/lutram.ys b/tests/arch/machxo2/lutram.ys
@@ -2,7 +2,7 @@ read_verilog ../common/lutram.v
 hierarchy -top lutram_1w1r
 proc
 memory -nomap
-equiv_opt -run :prove -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 -nowidelut
+equiv_opt -run :prove -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2
 memory
 opt -full
 

diff --git a/tests/arch/machxo2/mux.ys b/tests/arch/machxo2/mux.ys
@@ -3,7 +3,7 @@ design -save read
 
 hierarchy -top mux2
 proc
-equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 -nowidelut # equivalency check
+equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux2 # Constrain all select calls below inside the top module
 select -assert-count 1 t:LUT4
@@ -12,7 +12,7 @@ select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
 design -load read
 hierarchy -top mux4
 proc
-equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 -nowidelut # equivalency check
+equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux4 # Constrain all select calls below inside the top module
 select -assert-count 2 t:LUT4
@@ -22,7 +22,7 @@ select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
 design -load read
 hierarchy -top mux8
 proc
-equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 -nowidelut # equivalency check
+equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux8 # Constrain all select calls below inside the top module
 select -assert-count 5 t:LUT4
@@ -32,7 +32,7 @@ select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
 design -load read
 hierarchy -top mux16
 proc
-equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 -nowidelut # equivalency check
+equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux16 # Constrain all select calls below inside the top module
 select -assert-max 12 t:LUT4